89ea323250
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
220 lines
24 KiB
Text
220 lines
24 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 73131 # Simulator instruction rate (inst/s)
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host_mem_usage 199016 # Number of bytes of host memory used
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host_seconds 0.04 # Real time elapsed on the host
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host_tick_rate 490513834 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 2577 # Number of instructions simulated
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sim_seconds 0.000017 # Number of seconds simulated
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sim_ticks 17374000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 616 # number of overall hits
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system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 93 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use
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system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.dtb.accesses 717 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 709 # DTB hits
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system.cpu.dtb.misses 8 # DTB misses
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system.cpu.dtb.read_accesses 419 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 415 # DTB read hits
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system.cpu.dtb.read_misses 4 # DTB read misses
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system.cpu.dtb.write_accesses 298 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 294 # DTB write hits
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system.cpu.dtb.write_misses 4 # DTB write misses
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system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses
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system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 2423 # number of overall hits
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system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses
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system.cpu.icache.overall_misses 163 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use
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system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 2597 # ITB accesses
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system.cpu.itb.acv 0 # ITB acv
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system.cpu.itb.hits 2586 # ITB hits
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system.cpu.itb.misses 11 # ITB misses
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system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 0 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 245 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 34748 # number of cpu cycles simulated
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system.cpu.num_insts 2577 # Number of instructions executed
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system.cpu.num_refs 717 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
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---------- End Simulation Statistics ----------
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