935ba67b4f
SConscript:
Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
Fix paths.
configs/test/fs.py:
SimpleCPU -> AtomicSimpleCPU
Fix vmlinux path
cpu/simple/atomic.cc:
Fix suspendContext() so quiesce works.
Don't forget to checkForInterrupts().
cpu/simple/base.cc:
Minor fix to interrupt check code.
dev/ide_disk.hh:
Don't declare regStats() in header since it's not in
.cc file anymore (will need to add it back in when
stats are added back).
dev/io_device.cc:
Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
Set PCI config packet result to Success.
python/m5/objects/Root.py:
Add debug object to Root so things like break_cycles
can be set from command line.
--HG--
extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
215 lines
8.9 KiB
Python
215 lines
8.9 KiB
Python
from m5 import *
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import os
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from SysPaths import *
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# Base for tests is directory containing this file.
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test_base = os.path.dirname(__file__)
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linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
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class IdeControllerPciData(PciConfigData):
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VendorID = 0x8086
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DeviceID = 0x7111
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Command = 0x0
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Status = 0x280
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Revision = 0x0
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ClassCode = 0x01
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SubClassCode = 0x01
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ProgIF = 0x85
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BAR0 = 0x00000001
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BAR1 = 0x00000001
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BAR2 = 0x00000001
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BAR3 = 0x00000001
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BAR4 = 0x00000001
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BAR5 = 0x00000001
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InterruptLine = 0x1f
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InterruptPin = 0x01
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BAR0Size = '8B'
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BAR1Size = '4B'
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BAR2Size = '8B'
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BAR3Size = '4B'
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BAR4Size = '16B'
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class SinicPciData(PciConfigData):
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VendorID = 0x1291
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DeviceID = 0x1293
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = 0x00000000
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '64kB'
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class NSGigEPciData(PciConfigData):
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VendorID = 0x100B
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DeviceID = 0x0022
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = 0x00000001
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '256B'
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BAR1Size = '4kB'
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class LinuxRootDisk(IdeDisk):
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raw_image = RawDiskImage(image_file=linux_image, read_only=True)
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image = CowDiskImage(child=Parent.raw_image, read_only=False)
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class LinuxSwapDisk(IdeDisk):
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raw_image = RawDiskImage(image_file = disk('linux-bigswap2.img'),
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read_only=True)
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image = CowDiskImage(child = Parent.raw_image, read_only=False)
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class SpecwebFilesetDisk(IdeDisk):
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raw_image = RawDiskImage(image_file = disk('specweb-fileset.img'),
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read_only=True)
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image = CowDiskImage(child = Parent.raw_image, read_only=False)
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class BaseTsunami(Tsunami):
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cchip = TsunamiCChip(pio_addr=0x801a0000000)
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pchip = TsunamiPChip(pio_addr=0x80180000000)
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pciconfig = PciConfigAll(pio_addr=0x801fe000000)
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fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
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fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
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fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
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fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
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fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
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fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
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fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
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fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
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fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
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fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
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fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
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fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
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fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
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fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
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fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
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fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
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fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
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fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
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fake_ata1 = IsaFake(pio_addr=0x801fc000170)
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fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
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io = TsunamiIO(pio_addr=0x801fc000000)
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uart = Uart8250(pio_addr=0x801fc0003f8)
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ethernet = NSGigE(configdata=NSGigEPciData(),
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pci_bus=0, pci_dev=1, pci_func=0)
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etherint = NSGigEInt(device=Parent.ethernet)
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# ethernet = Sinic(configdata=SinicPciData(),
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# pci_bus=0, pci_dev=1, pci_func=0)
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# etherint = SinicInt(device=Parent.ethernet)
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console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
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# bridge = PciFake(configdata=BridgePciData(), pci_bus=0, pci_dev=2, pci_func=0)
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#class FreeBSDTsunami(BaseTsunami):
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# disk0 = FreeBSDRootDisk(delay='0us', driveID='master')
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# ide = IdeController(disks=[Parent.disk0],
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# configdata=IdeControllerPciData(),
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# pci_func=0, pci_dev=0, pci_bus=0)
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class LinuxTsunami(BaseTsunami):
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disk0 = LinuxRootDisk(driveID='master')
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disk1 = SpecwebFilesetDisk(driveID='slave')
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disk2 = LinuxSwapDisk(driveID='master')
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ide = IdeController(disks=[Parent.disk0, Parent.disk1, Parent.disk2],
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configdata=IdeControllerPciData(),
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pci_func=0, pci_dev=0, pci_bus=0)
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class LinuxAlphaSystem(LinuxAlphaSystem):
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magicbus = Bus(bus_id=0)
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magicbus2 = Bus(bus_id=1)
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bridge = Bridge()
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physmem = PhysicalMemory(range = AddrRange('128MB'))
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c0a = Connector(side_a=Parent.magicbus, side_b=Parent.bridge, side_b_name="side_a")
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c0b = Connector(side_a=Parent.magicbus2, side_b=Parent.bridge, side_b_name="side_b")
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c1 = Connector(side_a=Parent.physmem, side_b=Parent.magicbus2)
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tsunami = LinuxTsunami()
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c2 = Connector(side_a=Parent.tsunami.cchip, side_a_name='pio', side_b=Parent.magicbus)
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c3 = Connector(side_a=Parent.tsunami.pchip, side_a_name='pio', side_b=Parent.magicbus)
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c4 = Connector(side_a=Parent.tsunami.pciconfig, side_a_name='pio', side_b=Parent.magicbus)
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c5 = Connector(side_a=Parent.tsunami.fake_sm_chip, side_a_name='pio', side_b=Parent.magicbus)
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c6 = Connector(side_a=Parent.tsunami.ethernet, side_a_name='pio', side_b=Parent.magicbus)
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c6a = Connector(side_a=Parent.tsunami.ethernet, side_a_name='dma', side_b=Parent.magicbus)
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c7 = Connector(side_a=Parent.tsunami.fake_uart1, side_a_name='pio', side_b=Parent.magicbus)
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c8 = Connector(side_a=Parent.tsunami.fake_uart2, side_a_name='pio', side_b=Parent.magicbus)
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c9 = Connector(side_a=Parent.tsunami.fake_uart3, side_a_name='pio', side_b=Parent.magicbus)
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c10 = Connector(side_a=Parent.tsunami.fake_uart4, side_a_name='pio', side_b=Parent.magicbus)
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c11 = Connector(side_a=Parent.tsunami.ide, side_a_name='pio', side_b=Parent.magicbus)
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c13 = Connector(side_a=Parent.tsunami.ide, side_a_name='dma', side_b=Parent.magicbus)
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c12 = Connector(side_a=Parent.tsunami.fake_ppc, side_a_name='pio', side_b=Parent.magicbus)
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c14 = Connector(side_a=Parent.tsunami.fake_OROM, side_a_name='pio', side_b=Parent.magicbus)
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c16 = Connector(side_a=Parent.tsunami.fake_pnp_addr, side_a_name='pio', side_b=Parent.magicbus)
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c17 = Connector(side_a=Parent.tsunami.fake_pnp_write, side_a_name='pio', side_b=Parent.magicbus)
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c18 = Connector(side_a=Parent.tsunami.fake_pnp_read0, side_a_name='pio', side_b=Parent.magicbus)
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c19 = Connector(side_a=Parent.tsunami.fake_pnp_read1, side_a_name='pio', side_b=Parent.magicbus)
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c20 = Connector(side_a=Parent.tsunami.fake_pnp_read2, side_a_name='pio', side_b=Parent.magicbus)
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c21 = Connector(side_a=Parent.tsunami.fake_pnp_read3, side_a_name='pio', side_b=Parent.magicbus)
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c22 = Connector(side_a=Parent.tsunami.fake_pnp_read4, side_a_name='pio', side_b=Parent.magicbus)
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c23 = Connector(side_a=Parent.tsunami.fake_pnp_read5, side_a_name='pio', side_b=Parent.magicbus)
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c24 = Connector(side_a=Parent.tsunami.fake_pnp_read6, side_a_name='pio', side_b=Parent.magicbus)
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c25 = Connector(side_a=Parent.tsunami.fake_pnp_read7, side_a_name='pio', side_b=Parent.magicbus)
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c27 = Connector(side_a=Parent.tsunami.fake_ata0, side_a_name='pio', side_b=Parent.magicbus)
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c28 = Connector(side_a=Parent.tsunami.fake_ata1, side_a_name='pio', side_b=Parent.magicbus)
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c30 = Connector(side_a=Parent.tsunami.fb, side_a_name='pio', side_b=Parent.magicbus)
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c31 = Connector(side_a=Parent.tsunami.io, side_a_name='pio', side_b=Parent.magicbus)
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c32 = Connector(side_a=Parent.tsunami.uart, side_a_name='pio', side_b=Parent.magicbus)
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c33 = Connector(side_a=Parent.tsunami.console, side_a_name='pio', side_b=Parent.magicbus)
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raw_image = RawDiskImage(image_file=disk('linux-latest.img'),
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read_only=True)
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simple_disk = SimpleDisk(disk=Parent.raw_image)
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intrctrl = IntrControl()
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cpu = AtomicSimpleCPU(mem=Parent.magicbus2)
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sim_console = SimConsole(listener=ConsoleListener(port=3456))
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kernel = binary('vmlinux')
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pal = binary('ts_osfpal')
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console = binary('console')
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boot_osflags = 'root=/dev/hda1 console=ttyS0'
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# readfile = os.path.join(test_base, 'halt.sh')
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BaseCPU.itb = AlphaITB()
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BaseCPU.dtb = AlphaDTB()
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BaseCPU.system = Parent.any
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class TsunamiRoot(System):
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pass
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def DualRoot(ClientSystem, ServerSystem):
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self = Root()
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self.client = ClientSystem()
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self.server = ServerSystem()
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self.etherdump = EtherDump(file='ethertrace')
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self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
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int2 = Parent.server.tsunami.etherint[0],
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dump = Parent.etherdump)
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self.clock = '5GHz'
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return self
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root = DualRoot(ClientSystem = LinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
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ServerSystem = LinuxAlphaSystem(readfile=script('netperf-server.rcS')))
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