arch/alpha/isa_traits.hh: used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs so other archs. can use SimpleCPU arch/mips/SConscript: dont include common_syscall or tru64 arch/mips/faults.cc: arch/mips/faults.hh: arch/mips/isa/formats/unimp.isa: arch/mips/isa/formats/unknown.isa: Change Faults to new format arch/mips/isa/decoder.isa: Fix readMiscReg access Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants of the sll instruction so I may need to make a separte class of instructions to handle thse better arch/mips/isa/includes.isa: add isa_traits.hh and MipsISA included into every auto-gen file arch/mips/isa_traits.cc: create copyMiscRegs function... delete useless code arch/mips/isa_traits.hh: clean up for build arch/mips/linux_process.cc: mem is now getMemPort(), linux process objects now take in a system argument arch/mips/linux_process.hh: new argument for linux process arch/mips/process.cc: add system arch/mips/process.hh: add system variable cpu/cpu_exec_context.cc: Change AlphaISA to TheISA cpu/exec_context.hh: add readNextNPC and setNextNPC functions cpu/simple/cpu.cc: include isa_traits for namespace declariation cpu/simple/cpu.hh: PC & NPC access/modify functions arch/mips/utility.hh: file needed for compile --HG-- extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535
52 lines
2.2 KiB
C++
52 lines
2.2 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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output decoder {{
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std::string
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Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
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"unknown", machInst, OPCODE);
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}
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}};
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output exec {{
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Fault
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Unknown::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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panic("attempt to execute unknown instruction "
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"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
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return new UnimplementedOpcodeFault;
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}
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}};
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def format Unknown() {{
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decode_block = 'return new Unknown(machInst);\n'
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}};
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