5c4714c1a9
SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
209 lines
6 KiB
C++
209 lines
6 KiB
C++
//Todo:
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#ifndef __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
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#define __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/beta_cpu/alpha_full_cpu.hh"
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#include "cpu/beta_cpu/alpha_impl.hh"
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#include "cpu/inst_seq.hh"
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/**
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* Mostly implementation specific AlphaDynInst. It is templated in case there
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* are other implementations that are similar enough to be able to use this
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* class without changes. This is mainly useful if there are multiple similar
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* CPU implementations of the same ISA.
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*/
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template <class Impl>
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class AlphaDynInst : public BaseDynInst<Impl>
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{
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public:
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/** Typedef for the CPU. */
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typedef typename Impl::FullCPU FullCPU;
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/** Typedef to get the ISA. */
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typedef typename Impl::ISA ISA;
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/** Binary machine instruction type. */
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typedef typename ISA::MachInst MachInst;
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/** Memory address type. */
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typedef typename ISA::Addr Addr;
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/** Logical register index type. */
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typedef typename ISA::RegIndex RegIndex;
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/** Integer register index type. */
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typedef typename ISA::IntReg IntReg;
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enum {
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MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
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MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
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};
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public:
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/** BaseDynInst constructor given a binary instruction. */
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AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
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FullCPU *cpu);
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/** BaseDynInst constructor given a static inst pointer. */
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AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
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/** Executes the instruction. Why the hell did I put this here? */
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Fault execute()
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{
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this->fault = this->staticInst->execute(this, this->traceData);
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return this->fault;
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}
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public:
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uint64_t readUniq();
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void setUniq(uint64_t val);
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uint64_t readFpcr();
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void setFpcr(uint64_t val);
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#ifdef FULL_SYSTEM
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uint64_t readIpr(int idx, Fault &fault);
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Fault setIpr(int idx, uint64_t val);
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Fault hwrei();
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int readIntrFlag();
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void setIntrFlag(int val);
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bool inPalMode();
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void trap(Fault fault);
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bool simPalCheck(int palFunc);
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#else
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void syscall();
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#endif
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private:
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/** Physical register index of the destination registers of this
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* instruction.
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*/
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PhysRegIndex _destRegIdx[MaxInstDestRegs];
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/** Physical register index of the source registers of this
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* instruction.
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*/
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PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
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/** Physical register index of the previous producers of the
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* architected destinations.
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*/
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PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
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public:
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// The register accessor methods provide the index of the
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// instruction's operand (e.g., 0 or 1), not the architectural
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// register index, to simplify the implementation of register
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// renaming. We find the architectural register index by indexing
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// into the instruction's own operand index table. Note that a
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// raw pointer to the StaticInst is provided instead of a
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// ref-counted StaticInstPtr to redice overhead. This is fine as
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// long as these methods don't copy the pointer into any long-term
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// storage (which is pretty hard to imagine they would have reason
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// to do).
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uint64_t readIntReg(StaticInst<ISA> *si, int idx)
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{
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return this->cpu->readIntReg(_srcRegIdx[idx]);
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}
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float readFloatRegSingle(StaticInst<ISA> *si, int idx)
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{
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return this->cpu->readFloatRegSingle(_srcRegIdx[idx]);
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}
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double readFloatRegDouble(StaticInst<ISA> *si, int idx)
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{
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return this->cpu->readFloatRegDouble(_srcRegIdx[idx]);
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}
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uint64_t readFloatRegInt(StaticInst<ISA> *si, int idx)
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{
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return this->cpu->readFloatRegInt(_srcRegIdx[idx]);
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}
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/** @todo: Make results into arrays so they can handle multiple dest
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* registers.
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*/
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void setIntReg(StaticInst<ISA> *si, int idx, uint64_t val)
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{
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this->cpu->setIntReg(_destRegIdx[idx], val);
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this->instResult.integer = val;
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}
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void setFloatRegSingle(StaticInst<ISA> *si, int idx, float val)
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{
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this->cpu->setFloatRegSingle(_destRegIdx[idx], val);
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this->instResult.fp = val;
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}
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void setFloatRegDouble(StaticInst<ISA> *si, int idx, double val)
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{
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this->cpu->setFloatRegDouble(_destRegIdx[idx], val);
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this->instResult.dbl = val;
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}
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void setFloatRegInt(StaticInst<ISA> *si, int idx, uint64_t val)
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{
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this->cpu->setFloatRegInt(_destRegIdx[idx], val);
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this->instResult.integer = val;
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}
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/** Returns the physical register index of the i'th destination
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* register.
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*/
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PhysRegIndex renamedDestRegIdx(int idx) const
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{
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return _destRegIdx[idx];
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}
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/** Returns the physical register index of the i'th source register. */
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PhysRegIndex renamedSrcRegIdx(int idx) const
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{
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return _srcRegIdx[idx];
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}
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/** Returns the physical register index of the previous physical register
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* that remapped to the same logical register index.
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*/
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PhysRegIndex prevDestRegIdx(int idx) const
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{
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return _prevDestRegIdx[idx];
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}
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/** Renames a destination register to a physical register. Also records
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* the previous physical register that the logical register mapped to.
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*/
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void renameDestReg(int idx,
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PhysRegIndex renamed_dest,
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PhysRegIndex previous_rename)
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{
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_destRegIdx[idx] = renamed_dest;
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_prevDestRegIdx[idx] = previous_rename;
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}
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/** Renames a source logical register to the physical register which
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* has/will produce that logical register's result.
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* @todo: add in whether or not the source register is ready.
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*/
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void renameSrcReg(int idx, PhysRegIndex renamed_src)
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{
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_srcRegIdx[idx] = renamed_src;
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}
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public:
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Fault calcEA()
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{
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return this->staticInst->eaCompInst()->execute(this, this->traceData);
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}
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Fault memAccess()
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{
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return this->staticInst->memAccInst()->execute(this, this->traceData);
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}
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};
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#endif // __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
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