54b49f933a
base/traceflags.py:
removed TsunamiUart/TlaserUart and added a plain Uart
dev/alpha_console.cc:
updated for new simconsole
dev/platform.hh:
added a uart member to platform
dev/simconsole.cc:
dev/simconsole.hh:
removed lots of legacy code, it should all be ours now.
converted tabs to 8 spaces
added our copyright
dev/tsunami.cc:
uses simconsole.hh rather than console.hh
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
never needed console.hh
dev/tsunami_io.hh:
this does need eventq.hh and it just happend to be working whenn console.hh was
included everywhere
dev/tsunamireg.h:
added a couple more 8250/16550 uart defines
dev/uart.cc:
new uart code, rewritten to support both tlaser and tsunami (both a 8250 and 8530
uart).
dev/uart.hh:
updated for new uart, legacy code removed
--HG--
rename : dev/console.cc => dev/simconsole.cc
rename : dev/console.hh => dev/simconsole.hh
rename : dev/tsunami_uart.cc => dev/uart.cc
rename : dev/tsunami_uart.hh => dev/uart.hh
extra : convert_revision : e663352d49d4c2d3c95643030cf73c0e85ba2f08
294 lines
8.7 KiB
C++
294 lines
8.7 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Tsunami Fake I/O Space mapping including RTC/timer interrupts
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*/
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#ifndef __TSUNAMI_DMA_HH__
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#define __TSUNAMI_DMA_HH__
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#include "dev/io_device.hh"
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#include "base/range.hh"
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#include "dev/tsunami.hh"
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#include "sim/eventq.hh"
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/** How often the RTC interrupts */
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static const int RTC_RATE = 1024;
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/*
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* Tsunami I/O device is a catch all for all the south bridge stuff we care
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* to implement.
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*/
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class TsunamiIO : public PioDevice
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{
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private:
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/** The base address of this device */
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Addr addr;
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/** The size of mappad from the above address */
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static const Addr size = 0xff;
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struct tm tm;
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/** In Tsunami RTC only has two i/o ports one for data and one for address,
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* so you write the address and then read/write the data. This store the
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* address you are going to be reading from on a read.
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*/
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uint8_t RTCAddress;
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protected:
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/**
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* The ClockEvent is handles the PIT interrupts
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*/
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class ClockEvent : public Event
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{
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protected:
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/** how often the PIT fires */
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Tick interval;
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/** The mode of the PIT */
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uint8_t mode;
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/** The status of the PIT */
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uint8_t status;
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public:
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/**
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* Just set the mode to 0
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*/
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ClockEvent();
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/**
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* processs the timer event
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*/
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virtual void process();
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/**
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* Returns a description of this event
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* @return the description
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*/
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virtual const char *description();
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/**
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* Schedule a timer interrupt to occur sometime in the future.
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*/
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void Program(int count);
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/**
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* Write the mode bits of the PIT.
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* @param mode the new mode
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*/
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void ChangeMode(uint8_t mode);
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/**
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* The current PIT status.
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* @return the status of the PIT
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*/
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uint8_t Status();
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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/**
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* Process RTC timer events and generate interrupts appropriately.
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*/
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class RTCEvent : public Event
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{
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protected:
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/** A pointer back to tsunami to create interrupt the processor. */
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Tsunami* tsunami;
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public:
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/** RTC Event initializes the RTC event by scheduling an event
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* RTC_RATE times pre second. */
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RTCEvent(Tsunami* t);
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/**
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* Interrupth the processor and reschedule the event.
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* */
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virtual void process();
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/**
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* Return a description of this event.
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* @return a description
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*/
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virtual const char *description();
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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/** uip UpdateInProgess says that the rtc is updating, but we just fake it
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* by alternating it on every read of the bit since we are going to
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* override the loop_per_jiffy time that it is trying to use the UIP to
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* calculate.
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*/
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uint8_t uip;
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/** Mask of the PIC1 */
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uint8_t mask1;
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/** Mask of the PIC2 */
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uint8_t mask2;
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/** Mode of PIC1. Not used for anything */
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uint8_t mode1;
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/** Mode of PIC2. Not used for anything */
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uint8_t mode2;
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/** Raw PIC interrupt register before masking */
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uint8_t picr; //Raw PIC interrput register
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/** Is the pic interrupting right now or not. */
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bool picInterrupting;
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/** A pointer to the Tsunami device which be belong to */
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Tsunami *tsunami;
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/**
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* This timer is initilized, but after I wrote the code
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* it doesn't seem to be used again, and best I can tell
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* it too is not connected to any interrupt port
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*/
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ClockEvent timer0;
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/**
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* This timer is used to control the speaker, which
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* we normally could care less about, however it is
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* also used to calculated the clockspeed and hense
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* bogomips which is kinda important to the scheduler
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* so we need to implemnt it although after boot I can't
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* imagine we would be playing with the PC speaker much
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*/
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ClockEvent timer2;
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/** This is the event used to interrupt the cpu like an RTC. */
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RTCEvent rtc;
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/** The interval is set via two writes to the PIT.
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* This variable contains a flag as to how many writes have happened, and
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* the time so far.
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*/
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uint32_t timerData;
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public:
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/**
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* Return the freqency of the RTC
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* @return interrupt rate of the RTC
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*/
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Tick frequency() const { return RTC_RATE; }
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/**
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* Initialize all the data for devices supported by Tsunami I/O.
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* @param name name of this device.
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* @param t pointer back to the Tsunami object that we belong to.
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* @param init_time Time (as in seconds since 1970) to set RTC to.
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* @param a address we are mapped at.
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* @param mmu pointer to the memory controller that sends us events.
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*/
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TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
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Addr a, MemoryController *mmu, HierParams *hier, Bus *bus);
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/**
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* Create the tm struct from seconds since 1970
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*/
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void set_time(time_t t);
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/**
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* Process a read to one of the devices we are emulating.
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* @param req Contains the address to read from.
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* @param data A pointer to write the read data to.
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* @return The fault condition of the access.
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*/
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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/**
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* Process a write to one of the devices we emulate.
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* @param req Contains the address to write to.
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* @param data The data to write.
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* @return The fault condition of the access.
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*/
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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/**
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* Post an PIC interrupt to the CPU via the CChip
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* @param bitvector interrupt to post.
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*/
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void postPIC(uint8_t bitvector);
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/**
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* Clear a posted interrupt
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* @param bitvector interrupt to clear
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*/
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void clearPIC(uint8_t bitvector);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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Tick cacheAccess(MemReqPtr &req);
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};
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#endif // __TSUNAMI_IO_HH__
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