gem5/src/arch
Gabe Black 5b5e2fd6cd X86: Hide the irrelevant portions of the address components for load and store microops.
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extra : convert_revision : a5ac6fefa09882f0833537e23f1ac0477bc89bb9
2007-08-01 14:34:59 -07:00
..
alpha Add a flag to indicate an instruction triggers a syscall in SE mode. 2007-07-31 17:34:08 -07:00
mips MIPS: Cleaned up includes to break loops, and got rid of isa_traits.cc 2007-08-01 13:55:47 -07:00
sparc Add a flag to indicate an instruction triggers a syscall in SE mode. 2007-07-31 17:34:08 -07:00
x86 X86: Hide the irrelevant portions of the address components for load and store microops. 2007-08-01 14:34:59 -07:00
isa_parser.py Fixed line number accounting 2007-07-20 23:12:26 -07:00
isa_specific.hh Add build hooks for x86. 2007-03-03 16:01:48 +00:00
micro_asm.py Fix a problem where part of a microops parameters might be interpretted as an "ID", and also added support for symbols. 2007-06-21 15:26:01 +00:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript style: Check/Fix whitespace on SCons files 2007-07-28 16:49:20 -07:00