139 lines
5.1 KiB
Python
139 lines
5.1 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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#
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# Note: the cache latency is only used by the sequencer on fast path hits
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#
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class Cache(RubyCache):
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latency = 3
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def define_options(parser):
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return
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def create_system(options, system, piobus, dma_devices, ruby_system):
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if buildEnv['PROTOCOL'] != 'Network_test':
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panic("This script requires the Network_test protocol to be built.")
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cpu_sequencers = []
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#
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# The Garnet tester protocol does not support fs nor dma
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#
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assert(piobus == None)
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assert(dma_devices == [])
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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# listed before the directory nodes and directory nodes before dma nodes, etc.
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#
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l1_cntrl_nodes = []
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dir_cntrl_nodes = []
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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cntrl_count = 0
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for i in xrange(options.num_cpus):
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#
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# First create the Ruby objects associated with this cpu
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# Only one cache exists for this protocol, so by default use the L1D
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# config parameters.
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#
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cache = Cache(size = options.l1d_size,
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assoc = options.l1d_assoc)
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#
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# Only one unified L1 cache exists. Can cache instructions and data.
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#
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l1_cntrl = L1Cache_Controller(version = i,
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cntrl_id = cntrl_count,
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cacheMemory = cache,
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ruby_system = ruby_system)
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cpu_seq = RubySequencer(icache = cache,
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dcache = cache,
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physMemPort = system.physmem.port,
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physmem = system.physmem,
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using_network_tester = True,
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ruby_system = ruby_system)
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l1_cntrl.sequencer = cpu_seq
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if piobus != None:
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cpu_seq.pio_port = piobus.port
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exec("system.l1_cntrl%d = l1_cntrl" % i)
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#
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# Add controllers and sequencers to the appropriate lists
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#
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cpu_sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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cntrl_count += 1
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phys_mem_size = long(system.physmem.range.second) - \
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long(system.physmem.range.first) + 1
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mem_module_size = phys_mem_size / options.num_dirs
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for i in xrange(options.num_dirs):
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#
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# Create the Ruby objects associated with the directory controller
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#
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mem_cntrl = RubyMemoryControl(version = i)
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dir_size = MemorySize('0B')
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dir_size.value = mem_module_size
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dir_cntrl = Directory_Controller(version = i,
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cntrl_id = cntrl_count,
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directory = \
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RubyDirectoryMemory(version = i,
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size = dir_size),
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memBuffer = mem_cntrl,
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ruby_system = ruby_system)
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exec("system.dir_cntrl%d = dir_cntrl" % i)
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dir_cntrl_nodes.append(dir_cntrl)
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cntrl_count += 1
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all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes
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return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
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