1509 lines
172 KiB
Text
1509 lines
172 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.401343 # Number of seconds simulated
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sim_ticks 2401342505500 # Number of ticks simulated
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final_tick 2401342505500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 199955 # Simulator instruction rate (inst/s)
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host_op_rate 256803 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 7959007704 # Simulator tick rate (ticks/s)
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host_mem_usage 399904 # Number of bytes of host memory used
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host_seconds 301.71 # Real time elapsed on the host
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sim_insts 60329298 # Number of instructions simulated
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sim_ops 77481139 # Number of ops (including micro ops) simulated
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system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 502112 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 7093136 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 84928 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 676160 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 175680 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 1309048 # Number of bytes read from this memory
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system.physmem.bytes_read::total 124660776 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 502112 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 84928 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 175680 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 762720 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3745536 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 1490604 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu2.data 1325756 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6761352 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 14048 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 110864 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 1327 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 10565 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 2745 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 20467 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 14512410 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 58524 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 372651 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu2.data 331439 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 812478 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47814534 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 209096 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 2953821 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 35367 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 281576 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 73159 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 545132 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51912951 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 209096 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 35367 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 73159 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 317622 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1559768 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 620738 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu2.data 552090 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2815655 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1559768 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47814534 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 209096 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 3574559 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 35367 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 364636 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 73159 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 1097221 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 54728606 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 12618023 # Total number of read requests seen
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system.physmem.writeReqs 398732 # Total number of write requests seen
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system.physmem.cpureqs 54886 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 807553472 # Total number of bytes read from memory
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system.physmem.bytesWritten 25518848 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 102909560 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 2640668 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 2360 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 789126 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 788779 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 789203 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 789028 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 788746 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 788896 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 788935 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 788618 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 788026 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 788041 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 788281 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 788275 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 788125 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 788319 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 788742 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 24962 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 24831 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 24770 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 25056 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 24828 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 24649 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 24736 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 24783 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 25151 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 24834 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 24774 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 24883 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 25404 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 24880 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 24969 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 25222 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 14347 # Number of times wr buffer was full causing retry
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system.physmem.totGap 2400307282000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 14 # Categorize read packet sizes
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system.physmem.readPktSize::3 12582912 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 35097 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 381303 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 17429 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 815886 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 792065 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 797737 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 2998161 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2260870 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2261150 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2249588 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 49294 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 49195 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 91403 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 133606 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 91397 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 6927 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 6919 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 6911 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 6910 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2988 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2993 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2994 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 3016 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 3014 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 3013 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 3009 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 17346 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 17334 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 17330 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 17321 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 17317 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 17314 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 17308 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 17301 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 17296 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 17293 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::22 17291 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::23 14401 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 14393 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::25 14385 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 14359 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 14357 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 14355 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 14353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 14351 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 14349 # What write queue length does an incoming req see
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system.physmem.totQLat 277119182500 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 352940243750 # Sum of mem lat for all requests
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system.physmem.totBusLat 63090115000 # Total cycles spent in databus access
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system.physmem.totBankLat 12730946250 # Total cycles spent in bank access
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system.physmem.avgQLat 21962.17 # Average queueing delay per request
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system.physmem.avgBankLat 1008.95 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 27971.12 # Average memory access latency
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system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 42.86 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 2.71 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.15 # Average read queue length over time
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system.physmem.avgWrQLen 0.39 # Average write queue length over time
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system.physmem.readRowHits 12563435 # Number of row buffer hits during reads
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system.physmem.writeRowHits 392399 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes
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system.physmem.avgGap 184401.36 # Average gap between requests
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system.l2c.replacements 63248 # number of replacements
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system.l2c.tagsinuse 50357.471102 # Cycle average of tags in use
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system.l2c.total_refs 1749120 # Total number of references to valid blocks.
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system.l2c.sampled_refs 128641 # Sample count of references to valid blocks.
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system.l2c.avg_refs 13.596909 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 2374433885500 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::writebacks 36827.136068 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.inst 5149.319270 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.data 3787.835363 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.inst 800.097709 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.data 742.779862 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu2.dtb.walker 5.892734 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu2.inst 1445.756642 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu2.data 1597.659994 # Average occupied blocks per requestor
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system.l2c.occ_percent::writebacks 0.561938 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.inst 0.078572 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.data 0.057798 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.inst 0.012209 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.data 0.011334 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.dtb.walker 0.000090 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.inst 0.022060 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.data 0.024378 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::total 0.768394 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 8872 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 3222 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 463074 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 169165 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 2536 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 1092 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 132302 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 65381 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.dtb.walker 18053 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.itb.walker 4139 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 283993 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 138836 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1290665 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 597754 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 597754 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 60607 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 19371 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu2.data 33591 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 113569 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 8872 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 3222 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 463074 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 229772 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 2536 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 1092 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 132302 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 84752 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.dtb.walker 18053 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.itb.walker 4139 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 283993 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 172427 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1404234 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 8872 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 3222 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 463074 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 229772 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 2536 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 1092 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 132302 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 84752 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.dtb.walker 18053 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.itb.walker 4139 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 283993 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 172427 # number of overall hits
|
|
system.l2c.overall_hits::total 1404234 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 6388 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 1327 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 1186 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.dtb.walker 6 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 2745 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 2575 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 21663 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 1421 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 507 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 983 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 105230 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 9653 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 18483 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 133366 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 111618 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 1327 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 10839 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.dtb.walker 6 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 2745 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 21058 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 155029 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 111618 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 1327 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 10839 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.dtb.walker 6 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 2745 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 21058 # number of overall misses
|
|
system.l2c.overall_misses::total 155029 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 73983500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 68430000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 704500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.inst 174583500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.data 158774499 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 476544999 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 114500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu2.data 90500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 205000 # number of UpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 433747000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 983033500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 1416780500 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 73983500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 502177000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.dtb.walker 704500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 174583500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 1141807999 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 1893325499 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 73983500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 502177000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.dtb.walker 704500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 174583500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 1141807999 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 1893325499 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 8873 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 3224 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 470506 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 175553 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 2537 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 1092 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 133629 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 66567 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.dtb.walker 18059 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.itb.walker 4139 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.inst 286738 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.data 141411 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 1312328 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 597754 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 597754 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 1434 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 511 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 996 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 2941 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu2.data 4 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 165837 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 29024 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 52074 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 246935 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 8873 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 3224 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 470506 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 341390 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 2537 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 1092 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 133629 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 95591 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.dtb.walker 18059 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.itb.walker 4139 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 286738 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 193485 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 1559263 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 8873 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 3224 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 470506 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 341390 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 2537 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 1092 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 133629 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 95591 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.dtb.walker 18059 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.itb.walker 4139 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 286738 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 193485 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 1559263 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000620 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015796 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.036388 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.009930 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.017817 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000332 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.inst 0.009573 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.data 0.018209 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.016507 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990934 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992172 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.986948 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.989799 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.634539 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.332587 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 0.354937 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.540085 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000620 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.015796 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.326952 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.009930 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.113389 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000332 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.009573 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.108835 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.099425 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000620 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.015796 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.326952 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.009930 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.113389 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000332 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.009573 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.108835 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.099425 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55752.449133 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 57698.145025 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 117416.666667 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 63600.546448 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.data 61659.999612 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 21998.107326 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 225.838264 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 92.065107 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 70.422535 # average UpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44933.906558 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53185.819402 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 10623.251053 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 55752.449133 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 46330.565550 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 117416.666667 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 63600.546448 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 54222.053329 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 12212.718259 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 55752.449133 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 46330.565550 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 117416.666667 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 63600.546448 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 54222.053329 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 12212.718259 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 58524 # number of writebacks
|
|
system.l2c.writebacks::total 58524 # number of writebacks
|
|
system.l2c.ReadReq_mshr_hits::cpu2.data 9 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.data 9 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.data 9 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 1327 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 1186 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 6 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.inst 2745 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.data 2566 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 7831 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 507 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 983 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 1490 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 9653 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 18483 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 28136 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 1327 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 10839 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.dtb.walker 6 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 2745 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 21049 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 35967 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 1327 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 10839 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.dtb.walker 6 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 2745 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 21049 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 35967 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56251 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 57336577 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 53623186 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 628006 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 140373172 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 126408652 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 378425844 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5102987 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9830983 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 14933970 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 313563138 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 752583812 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 1066146950 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 57336577 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 367186324 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 628006 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 140373172 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 878992464 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 1444572794 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56251 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 57336577 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 367186324 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 628006 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 140373172 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 878992464 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 1444572794 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25255173500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26538454761 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 51793628261 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 643402864 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9819118436 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 10462521300 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25898576364 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36357573197 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 62256149561 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009930 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017817 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000332 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009573 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018146 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.005967 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992172 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.986948 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.506630 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.332587 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.354937 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.113941 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009930 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.113389 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000332 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009573 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.108789 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.023067 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009930 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.113389 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000332 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009573 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.108789 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.023067 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43207.669179 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45213.478921 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 104667.666667 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 51137.767577 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 49262.919719 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 48324.076619 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10065.063116 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10022.798658 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32483.490935 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40717.622247 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 37892.626884 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43207.669179 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33876.402251 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 104667.666667 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51137.767577 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41759.345527 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 40163.838908 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43207.669179 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33876.402251 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 104667.666667 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51137.767577 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41759.345527 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 40163.838908 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 8064741 # DTB read hits
|
|
system.cpu0.dtb.read_misses 6215 # DTB read misses
|
|
system.cpu0.dtb.write_hits 6627061 # DTB write hits
|
|
system.cpu0.dtb.write_misses 2040 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 690 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 5695 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 8070956 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 6629101 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 14691802 # DTB hits
|
|
system.cpu0.dtb.misses 8255 # DTB misses
|
|
system.cpu0.dtb.accesses 14700057 # DTB accesses
|
|
system.cpu0.itb.inst_hits 32689341 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 3490 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 690 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2596 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 32692831 # ITB inst accesses
|
|
system.cpu0.itb.hits 32689341 # DTB hits
|
|
system.cpu0.itb.misses 3490 # DTB misses
|
|
system.cpu0.itb.accesses 32692831 # DTB accesses
|
|
system.cpu0.numCycles 114004049 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 32197863 # Number of instructions committed
|
|
system.cpu0.committedOps 42390807 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 37541776 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 5152 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 1189364 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 4237827 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 37541776 # number of integer instructions
|
|
system.cpu0.num_fp_insts 5152 # number of float instructions
|
|
system.cpu0.num_int_register_reads 191249726 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 39627279 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 3662 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 15356244 # number of memory refs
|
|
system.cpu0.num_load_insts 8432602 # Number of load instructions
|
|
system.cpu0.num_store_insts 6923642 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 13418877123.276752 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles -13304873074.276752 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction -116.705268 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 117.705268 # Percentage of idle cycles
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed
|
|
system.cpu0.icache.replacements 891776 # number of replacements
|
|
system.cpu0.icache.tagsinuse 511.602850 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 44220417 # Total number of references to valid blocks.
|
|
system.cpu0.icache.sampled_refs 892288 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.avg_refs 49.558458 # Average number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 8123363500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 478.597837 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_blocks::cpu1.inst 17.659572 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_blocks::cpu2.inst 15.345442 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.934761 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::cpu1.inst 0.034491 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::cpu2.inst 0.029972 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 32220796 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 8246178 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu2.inst 3753443 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 44220417 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 32220796 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 8246178 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu2.inst 3753443 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 44220417 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 32220796 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 8246178 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu2.inst 3753443 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 44220417 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 471225 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 133904 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu2.inst 311110 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 916239 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 471225 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 133904 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu2.inst 311110 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 916239 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 471225 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 133904 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu2.inst 311110 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 916239 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1804984500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4146410986 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 5951395486 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 1804984500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu2.inst 4146410986 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 5951395486 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 1804984500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu2.inst 4146410986 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 5951395486 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32692021 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 8380082 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu2.inst 4064553 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 45136656 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 32692021 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 8380082 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu2.inst 4064553 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 45136656 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 32692021 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 8380082 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu2.inst 4064553 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 45136656 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014414 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015979 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076542 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.020299 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014414 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015979 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076542 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.020299 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014414 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015979 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076542 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.020299 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.690674 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13327.797197 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 6495.461867 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13479.690674 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13327.797197 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 6495.461867 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13479.690674 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13327.797197 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 6495.461867 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 2817 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 194 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.520619 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23939 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 23939 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu2.inst 23939 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 23939 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu2.inst 23939 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 23939 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 133904 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287171 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 421075 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 133904 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu2.inst 287171 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 421075 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 133904 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu2.inst 287171 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 421075 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1537176500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3381635486 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4918811986 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1537176500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3381635486 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 4918811986 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1537176500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3381635486 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 4918811986 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015979 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070653 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009329 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015979 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070653 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.009329 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015979 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070653 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.009329 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11479.690674 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11775.685867 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11681.557884 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11479.690674 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11775.685867 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11681.557884 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11479.690674 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11775.685867 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11681.557884 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.replacements 629954 # number of replacements
|
|
system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use
|
|
system.cpu0.dcache.total_refs 23213851 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.sampled_refs 630466 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.avg_refs 36.820147 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 495.756165 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_blocks::cpu1.data 9.709007 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_blocks::cpu2.data 6.531944 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.968274 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::cpu1.data 0.018963 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::cpu2.data 0.012758 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6946152 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 1881152 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu2.data 4479308 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 13306612 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 5948925 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 1341191 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu2.data 2128617 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 9418733 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131368 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34012 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72748 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 238128 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137743 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35737 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73913 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 247393 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 12895077 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 3222343 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu2.data 6607925 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 22725345 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 12895077 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 3222343 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu2.data 6607925 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 22725345 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 169178 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 64842 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu2.data 284494 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 518514 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 167271 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 29535 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu2.data 600821 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 797627 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6375 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1725 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3870 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 11970 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 336449 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 94377 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu2.data 885315 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1316141 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 336449 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 94377 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu2.data 885315 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1316141 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 903782500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4105019000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 5008801500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 727658500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18527388398 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 19255046898 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22582000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52040000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 74622000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 52000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 52000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 1631441000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu2.data 22632407398 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 24263848398 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 1631441000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu2.data 22632407398 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 24263848398 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7115330 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1945994 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4763802 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 13825126 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 6116196 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1370726 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2729438 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 10216360 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137743 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35737 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76618 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 250098 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137743 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35737 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73917 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 247397 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 13231526 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 3316720 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu2.data 7493240 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 24041486 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 13231526 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 3316720 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu2.data 7493240 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 24041486 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023777 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033321 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059720 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.037505 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027349 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021547 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220126 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.078074 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046282 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048269 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050510 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047861 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000016 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025428 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028455 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118148 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.054745 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025428 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028455 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118148 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.054745 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13938.226767 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14429.193586 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 9659.915644 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24637.159303 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30836.785662 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 24140.415129 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13091.014493 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13447.028424 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6234.085213 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17286.425718 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25564.242555 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 18435.599528 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17286.425718 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25564.242555 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 18435.599528 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 10180 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 1987 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 1115 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 42 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.130045 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 47.309524 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 597754 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 597754 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146487 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 146487 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 547791 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 547791 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 426 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 426 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu2.data 694278 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 694278 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu2.data 694278 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 694278 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 64842 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 138007 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 202849 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29535 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53030 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 82565 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1725 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3444 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5169 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 94377 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu2.data 191037 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 285414 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 94377 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 191037 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 285414 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 774098500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1795767000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2569865500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 668588500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1433658493 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2102246993 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19132000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40258500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59390500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 44000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1442687000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3229425493 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 4672112493 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1442687000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3229425493 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 4672112493 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27590939000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28973644000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56564583000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1276412500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14137928134 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15414340634 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28867351500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43111572134 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71978923634 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033321 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028970 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014672 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021547 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019429 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008082 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048269 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044950 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020668 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.011872 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.011872 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11938.226767 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13012.144312 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12668.859595 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22637.159303 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27034.857496 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25461.720983 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.014493 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11689.459930 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11489.746566 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 2161402 # DTB read hits
|
|
system.cpu1.dtb.read_misses 2114 # DTB read misses
|
|
system.cpu1.dtb.write_hits 1457218 # DTB write hits
|
|
system.cpu1.dtb.write_misses 386 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 41 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 2163516 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 1457604 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 3618620 # DTB hits
|
|
system.cpu1.dtb.misses 2500 # DTB misses
|
|
system.cpu1.dtb.accesses 3621120 # DTB accesses
|
|
system.cpu1.itb.inst_hits 8380082 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 1132 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 8381214 # ITB inst accesses
|
|
system.cpu1.itb.hits 8380082 # DTB hits
|
|
system.cpu1.itb.misses 1132 # DTB misses
|
|
system.cpu1.itb.accesses 8381214 # DTB accesses
|
|
system.cpu1.numCycles 574618954 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 8175033 # Number of instructions committed
|
|
system.cpu1.committedOps 10410069 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 9322021 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 315375 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 1140852 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 9322021 # number of integer instructions
|
|
system.cpu1.num_fp_insts 1998 # number of float instructions
|
|
system.cpu1.num_int_register_reads 53738545 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 10097471 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 3791152 # number of memory refs
|
|
system.cpu1.num_load_insts 2256757 # Number of load instructions
|
|
system.cpu1.num_store_insts 1534395 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 532868716.793879 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 41750237.206121 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.072657 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.927343 # Percentage of idle cycles
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu2.branchPred.lookups 4722397 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 3838487 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 221435 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 2952816 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 2527233 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 85.587216 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 411089 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 21408 # Number of incorrect RAS predictions.
|
|
system.cpu2.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dtb.read_hits 10881575 # DTB read hits
|
|
system.cpu2.dtb.read_misses 22640 # DTB read misses
|
|
system.cpu2.dtb.write_hits 3277177 # DTB write hits
|
|
system.cpu2.dtb.write_misses 5849 # DTB write misses
|
|
system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
|
|
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dtb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dtb.flush_entries 2319 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dtb.align_faults 814 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dtb.prefetch_faults 160 # Number of TLB faults due to prefetch
|
|
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dtb.read_accesses 10904215 # DTB read accesses
|
|
system.cpu2.dtb.write_accesses 3283026 # DTB write accesses
|
|
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dtb.hits 14158752 # DTB hits
|
|
system.cpu2.dtb.misses 28489 # DTB misses
|
|
system.cpu2.dtb.accesses 14187241 # DTB accesses
|
|
system.cpu2.itb.inst_hits 4065885 # ITB inst hits
|
|
system.cpu2.itb.inst_misses 4502 # ITB inst misses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed
|
|
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.itb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
|
|
system.cpu2.itb.flush_entries 1576 # Number of entries that have been flushed from TLB
|
|
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.itb.perms_faults 1005 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.inst_accesses 4070387 # ITB inst accesses
|
|
system.cpu2.itb.hits 4065885 # DTB hits
|
|
system.cpu2.itb.misses 4502 # DTB misses
|
|
system.cpu2.itb.accesses 4070387 # DTB accesses
|
|
system.cpu2.numCycles 88259873 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 9453176 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 32426467 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 4722397 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 2938322 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 6835194 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 1814499 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.TlbCycles 51467 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu2.fetch.BlockedCycles 18689225 # Number of cycles fetch has spent blocked
|
|
system.cpu2.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.PendingDrainCycles 953 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu2.fetch.PendingTrapStallCycles 32914 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.PendingQuiesceStallCycles 708494 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu2.fetch.IcacheWaitRetryStallCycles 306 # Number of stall cycles due to full MSHR
|
|
system.cpu2.fetch.CacheLines 4064555 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 309850 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.ItlbSquashes 1926 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 37018169 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.050897 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.436881 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 30188064 81.55% 81.55% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 383346 1.04% 82.58% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 510640 1.38% 83.96% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 813031 2.20% 86.16% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 657801 1.78% 87.94% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 343878 0.93% 88.87% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 1012409 2.73% 91.60% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 238466 0.64% 92.25% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 2870534 7.75% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 37018169 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.053506 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 0.367398 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 10067654 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 19275483 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 6184949 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 295259 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 1193811 # Number of cycles decode is squashing
|
|
system.cpu2.decode.BranchResolved 613325 # Number of times decode resolved a branch
|
|
system.cpu2.decode.BranchMispred 53657 # Number of times decode detected a branch misprediction
|
|
system.cpu2.decode.DecodedInsts 36756215 # Number of instructions handled by decode
|
|
system.cpu2.decode.SquashedInsts 182103 # Number of squashed instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 1193811 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 10642239 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 6572797 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 11156885 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 5885889 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 1565553 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 34514239 # Number of instructions processed by rename
|
|
system.cpu2.rename.ROBFullEvents 2456 # Number of times rename has blocked due to ROB full
|
|
system.cpu2.rename.IQFullEvents 419835 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LSQFullEvents 882809 # Number of times rename has blocked due to LSQ full
|
|
system.cpu2.rename.FullRegisterEvents 92 # Number of times there has been no free registers
|
|
system.cpu2.rename.RenamedOperands 37003284 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 157776579 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 157748805 # Number of integer rename lookups
|
|
system.cpu2.rename.fp_rename_lookups 27774 # Number of floating rename lookups
|
|
system.cpu2.rename.CommittedMaps 25809996 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 11193287 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 230807 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 207161 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 3357083 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 6535673 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 3850744 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 536963 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 792176 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 31747463 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 511528 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 34289699 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 55083 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 7395646 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 19879544 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 155324 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 37018169 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 0.926294 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.580927 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 24442328 66.03% 66.03% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 3909913 10.56% 76.59% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 2354045 6.36% 82.95% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 1974122 5.33% 88.28% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 2799200 7.56% 95.84% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 884316 2.39% 98.23% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 484064 1.31% 99.54% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 134882 0.36% 99.90% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 35299 0.10% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 37018169 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 18550 1.21% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 1408407 91.61% 92.81% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 110486 7.19% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 61448 0.18% 0.18% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 19376629 56.51% 56.69% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 26012 0.08% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 381 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 11380471 33.19% 89.95% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 3444734 10.05% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 34289699 # Type of FU issued
|
|
system.cpu2.iq.rate 0.388508 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 1537443 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.044837 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 107211457 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 39659859 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 27420215 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 6989 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 3825 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 3150 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 35761973 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 3721 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 208327 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 1579914 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 1893 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 9373 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 582518 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 5363105 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 352533 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 1193811 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 4877812 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 91796 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 32340028 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 60265 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 6535673 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 3850744 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 369403 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 31610 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 2472 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 9373 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 105135 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 88586 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 193721 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 33297921 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 11093060 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 991778 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 81037 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 14504508 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 3695173 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 3411448 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 0.377271 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 32878469 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 27423365 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 15687848 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 28539684 # num instructions consuming a value
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.wb_rate 0.310712 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.549685 # average fanout of values written-back
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.commit.commitSquashedInsts 7335381 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 356204 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 168508 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 35824220 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 0.690433 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 1.719118 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 27176930 75.86% 75.86% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 4185525 11.68% 87.55% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 1261410 3.52% 91.07% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 649563 1.81% 92.88% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 571804 1.60% 94.48% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 316250 0.88% 95.36% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 400543 1.12% 96.48% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 292091 0.82% 97.29% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 970104 2.71% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 35824220 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 20010366 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 24734227 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 8223985 # Number of memory references committed
|
|
system.cpu2.commit.loads 4955759 # Number of loads committed
|
|
system.cpu2.commit.membars 94186 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 3169280 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 3103 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 21954082 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 294910 # Number of function calls committed.
|
|
system.cpu2.commit.bw_lim_events 970104 # number cycles where commit BW limit reached
|
|
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu2.rob.rob_reads 66398809 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 65374131 # The number of ROB writes
|
|
system.cpu2.timesIdled 360148 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 51241704 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 3567295976 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 19956402 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 24680263 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.committedInsts_total 19956402 # Number of Instructions Simulated
|
|
system.cpu2.cpi 4.422635 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 4.422635 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 0.226110 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 0.226110 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 153855471 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 29258344 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_reads 22383 # number of floating regfile reads
|
|
system.cpu2.fp_regfile_writes 20838 # number of floating regfile writes
|
|
system.cpu2.misc_regfile_reads 9035132 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 240694 # number of misc regfile writes
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981038235668 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 981038235668 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981038235668 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 981038235668 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|