24da30e317
This basically means changing all #include statements and changing autogenerated code so that it generates the correct paths. Because slicc generates #includes, I had to hard code the include paths to mem/protocol.
126 lines
4.5 KiB
C++
126 lines
4.5 KiB
C++
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id$
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*
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* Description: Common base class for a machine chip.
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*
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*/
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#ifndef ABSTRACT_CHIP_H
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#define ABSTRACT_CHIP_H
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#include "mem/ruby/common/Global.hh"
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#include "mem/ruby/system/NodeID.hh"
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#include "mem/ruby/config/RubyConfig.hh"
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#include "mem/protocol/L1Cache_Entry.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/gems_common/Vector.hh"
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class Network;
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class Sequencer;
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class StoreBuffer;
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class ENTRY;
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class MessageBuffer;
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class CacheRecorder;
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class TransactionInterfaceManager;
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template<class ENTRY> class CacheMemory;
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class AbstractChip {
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public:
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// Constructors
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AbstractChip(NodeID chip_number, Network* net_ptr);
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// Destructor, prevent from being instantiated
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virtual ~AbstractChip() = 0;
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// Public Methods
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NodeID getID() const { return m_id; };
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Network* getNetwork() const { return m_net_ptr; };
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Sequencer* getSequencer(int index) const { return m_L1Cache_sequencer_vec[index]; };
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TransactionInterfaceManager* getTransactionInterfaceManager(int index) const { return m_L1Cache_xact_mgr_vec[index]; };
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void setTransactionInterfaceManager(TransactionInterfaceManager* manager, int index) { m_L1Cache_xact_mgr_vec[index] = manager; }
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// used when CHECK_COHERENCE is enabled. See RubySystem::checkGlobalCoherence()
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virtual bool isBlockExclusive(const Address& addr) const { return false; }
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virtual bool isBlockShared(const Address& addr) const { return false; }
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// cache dump functions
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virtual void recordCacheContents(CacheRecorder& tr) const = 0;
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virtual void dumpCaches(ostream& out) const = 0;
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virtual void dumpCacheData(ostream& out) const = 0;
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virtual void printConfig(ostream& out) = 0;
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virtual void print(ostream& out) const = 0;
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// pulic data structures
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Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L1DcacheMemory_vec;
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Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L1IcacheMemory_vec;
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Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_cacheMemory_vec;
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Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L2cacheMemory_vec;
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Vector < CacheMemory<L1Cache_Entry>* > m_L2Cache_L2cacheMemory_vec;
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// added so that the prefetcher and sequencer can access the L1 and L2 request queues
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Vector < MessageBuffer* > m_L1Cache_optionalQueue_vec;
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Vector < MessageBuffer* >m_L1Cache_mandatoryQueue_vec;
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// TSO storebuffer
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Vector < StoreBuffer* > m_L1Cache_storeBuffer_vec;
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// TM transaction manager
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Vector < TransactionInterfaceManager* > m_L1Cache_xact_mgr_vec;
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protected:
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// Data Members (m_ prefix)
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NodeID m_id; // Chip id
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Network* m_net_ptr; // Points to the Network simulator
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Vector < Sequencer* > m_L1Cache_sequencer_vec; // All chip should have a sequencer
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};
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// Output operator declaration
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ostream& operator<<(ostream& out, const AbstractChip& obj);
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// ******************* Definitions *******************
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// Output operator definition
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extern inline
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ostream& operator<<(ostream& out, const AbstractChip& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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#endif //ABSTRACT_CHIP_H
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