2147 lines
246 KiB
Plaintext
2147 lines
246 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.403670 # Number of seconds simulated
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sim_ticks 2403669993000 # Number of ticks simulated
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final_tick 2403669993000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 205695 # Simulator instruction rate (inst/s)
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host_op_rate 264190 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 8195476126 # Simulator tick rate (ticks/s)
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host_mem_usage 425360 # Number of bytes of host memory used
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host_seconds 293.29 # Real time elapsed on the host
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sim_insts 60328724 # Number of instructions simulated
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sim_ops 77484808 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 512584 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 7062488 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 64448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 676736 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 184896 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 1338016 # Number of bytes read from this memory
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system.physmem.bytes_read::total 124659200 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 512584 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 64448 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 184896 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 761928 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3742720 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 1298604 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu2.data 1557912 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6758536 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 14221 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 110387 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 1007 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 10574 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 2889 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 20914 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 14512391 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 58480 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 324651 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu2.data 389478 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 812434 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47768235 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 213251 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 2938210 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 26812 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 281543 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 76922 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 556655 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51862028 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 213251 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 26812 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 76922 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 316985 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1557086 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 540259 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 66274 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu2.data 648139 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2811757 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1557086 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47768235 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 213251 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 3478469 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 26812 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 347816 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 76922 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 1204794 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 54673785 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 13478692 # Number of read requests accepted
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system.physmem.writeReqs 446310 # Number of write requests accepted
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system.physmem.readBursts 13478692 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 446310 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 862636288 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 2859584 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 109811232 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 2805660 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 401628 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 2353 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 837730 # Per bank write bursts
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system.physmem.perBankRdBursts::1 837377 # Per bank write bursts
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system.physmem.perBankRdBursts::2 837570 # Per bank write bursts
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system.physmem.perBankRdBursts::3 838005 # Per bank write bursts
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system.physmem.perBankRdBursts::4 839135 # Per bank write bursts
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system.physmem.perBankRdBursts::5 839829 # Per bank write bursts
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system.physmem.perBankRdBursts::6 839954 # Per bank write bursts
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system.physmem.perBankRdBursts::7 841188 # Per bank write bursts
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system.physmem.perBankRdBursts::8 842692 # Per bank write bursts
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system.physmem.perBankRdBursts::9 845268 # Per bank write bursts
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system.physmem.perBankRdBursts::10 845422 # Per bank write bursts
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system.physmem.perBankRdBursts::11 845904 # Per bank write bursts
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system.physmem.perBankRdBursts::12 847097 # Per bank write bursts
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system.physmem.perBankRdBursts::13 848027 # Per bank write bursts
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system.physmem.perBankRdBursts::14 846853 # Per bank write bursts
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system.physmem.perBankRdBursts::15 846641 # Per bank write bursts
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system.physmem.perBankWrBursts::0 2732 # Per bank write bursts
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system.physmem.perBankWrBursts::1 2567 # Per bank write bursts
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system.physmem.perBankWrBursts::2 2586 # Per bank write bursts
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system.physmem.perBankWrBursts::3 3040 # Per bank write bursts
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system.physmem.perBankWrBursts::4 3458 # Per bank write bursts
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system.physmem.perBankWrBursts::5 3199 # Per bank write bursts
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system.physmem.perBankWrBursts::6 2529 # Per bank write bursts
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system.physmem.perBankWrBursts::7 2312 # Per bank write bursts
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system.physmem.perBankWrBursts::8 2235 # Per bank write bursts
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system.physmem.perBankWrBursts::9 2402 # Per bank write bursts
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system.physmem.perBankWrBursts::10 2375 # Per bank write bursts
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system.physmem.perBankWrBursts::11 2809 # Per bank write bursts
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system.physmem.perBankWrBursts::12 3726 # Per bank write bursts
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system.physmem.perBankWrBursts::13 3500 # Per bank write bursts
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system.physmem.perBankWrBursts::14 2647 # Per bank write bursts
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system.physmem.perBankWrBursts::15 2564 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 2402634752000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 8 # Read request sizes (log2)
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system.physmem.readPktSize::3 13443296 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 35388 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 429303 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 17007 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 975684 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 953327 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 947696 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 3279847 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2361574 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2361279 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2377764 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 45945 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 51807 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 17784 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 17782 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 17747 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 17627 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 17611 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 17604 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 17597 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 17 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2021 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2411 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2033 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 2231 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 2279 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 2018 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 2013 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 2034 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1987 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1980 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1972 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1967 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1962 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1962 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1951 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1954 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 1961 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 1959 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 1951 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 1942 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 2052 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 58 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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|
system.physmem.bytesPerActivate::samples 48746 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 17755.207812 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 3162.737998 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 18340.275925 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-71 8642 17.73% 17.73% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::128-135 4876 10.00% 27.73% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::192-199 980 2.01% 29.74% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::256-263 745 1.53% 31.27% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::320-327 418 0.86% 32.13% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::384-391 375 0.77% 32.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::448-455 281 0.58% 33.47% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::512-519 311 0.64% 34.11% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::576-583 181 0.37% 34.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-647 171 0.35% 34.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::704-711 151 0.31% 35.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-775 290 0.59% 35.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::832-839 88 0.18% 35.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-903 76 0.16% 36.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::960-967 42 0.09% 36.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1031 366 0.75% 36.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1088-1095 30 0.06% 36.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1152-1159 31 0.06% 37.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1216-1223 22 0.05% 37.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1280-1287 117 0.24% 37.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1344-1351 19 0.04% 37.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1408-1415 158 0.32% 37.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1472-1479 20 0.04% 37.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1536-1543 128 0.26% 37.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1600-1607 11 0.02% 38.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1664-1671 28 0.06% 38.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1728-1735 10 0.02% 38.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1792-1799 148 0.30% 38.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1856-1863 9 0.02% 38.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1920-1927 16 0.03% 38.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1984-1991 10 0.02% 38.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2048-2055 383 0.79% 39.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2176-2183 7 0.01% 39.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2240-2247 5 0.01% 39.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2304-2311 66 0.14% 39.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2368-2375 1 0.00% 39.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2432-2439 3 0.01% 39.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2496-2503 4 0.01% 39.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2560-2567 69 0.14% 39.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2624-2631 2 0.00% 39.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2688-2695 6 0.01% 39.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2752-2759 3 0.01% 39.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2816-2823 75 0.15% 39.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2880-2887 2 0.00% 39.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2944-2951 8 0.02% 39.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3008-3015 2 0.00% 39.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3072-3079 346 0.71% 40.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3200-3207 4 0.01% 40.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3264-3271 4 0.01% 40.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3328-3335 130 0.27% 40.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3392-3399 5 0.01% 40.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3456-3463 2 0.00% 40.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3520-3527 3 0.01% 40.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3584-3591 69 0.14% 40.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3648-3655 1 0.00% 40.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712-3719 8 0.02% 40.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776-3783 5 0.01% 40.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3840-3847 77 0.16% 41.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3911 8 0.02% 41.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-3975 4 0.01% 41.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032-4039 6 0.01% 41.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4103 331 0.68% 41.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4167 5 0.01% 41.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4231 3 0.01% 41.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4295 5 0.01% 41.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352-4359 190 0.39% 42.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4416-4423 12 0.02% 42.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4487 4 0.01% 42.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4544-4551 3 0.01% 42.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4615 36 0.07% 42.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4672-4679 4 0.01% 42.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4736-4743 2 0.00% 42.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800-4807 4 0.01% 42.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4871 136 0.28% 42.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928-4935 1 0.00% 42.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056-5063 2 0.00% 42.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5127 260 0.53% 43.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5184-5191 1 0.00% 43.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5248-5255 3 0.01% 43.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5312-5319 4 0.01% 43.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5383 67 0.14% 43.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5447 4 0.01% 43.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5511 3 0.01% 43.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5568-5575 3 0.01% 43.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5632-5639 70 0.14% 43.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5760-5767 2 0.00% 43.53% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5824-5831 4 0.01% 43.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5895 103 0.21% 43.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5952-5959 1 0.00% 43.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6023 1 0.00% 43.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6080-6087 9 0.02% 43.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6151 324 0.66% 44.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6272-6279 6 0.01% 44.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6407 4 0.01% 44.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6464-6471 4 0.01% 44.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6528-6535 5 0.01% 44.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6663 69 0.14% 44.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6727 2 0.00% 44.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6784-6791 7 0.01% 44.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6848-6855 1 0.00% 44.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6912-6919 3 0.01% 44.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6976-6983 3 0.01% 44.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7047 2 0.00% 44.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7104-7111 1 0.00% 44.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7175 295 0.61% 45.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7232-7239 2 0.00% 45.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7303 2 0.00% 45.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7360-7367 10 0.02% 45.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7552-7559 2 0.00% 45.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7680-7687 128 0.26% 45.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7943 1 0.00% 45.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8199 539 1.11% 46.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8448-8455 1 0.00% 46.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8704-8711 128 0.26% 46.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9216-9223 294 0.60% 47.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9472-9479 1 0.00% 47.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9600-9607 1 0.00% 47.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9728-9735 65 0.13% 47.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10240-10247 320 0.66% 48.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10496-10503 64 0.13% 48.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10752-10759 64 0.13% 48.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11008-11015 64 0.13% 48.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11264-11271 256 0.53% 49.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11520-11527 129 0.26% 49.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11776-11783 31 0.06% 49.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12032-12039 181 0.37% 49.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12288-12295 323 0.66% 50.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12544-12551 68 0.14% 50.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12800-12807 64 0.13% 50.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12864-12871 1 0.00% 50.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13056-13063 126 0.26% 51.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13248-13255 1 0.00% 51.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13312-13319 342 0.70% 51.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13568-13575 68 0.14% 51.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13824-13831 65 0.13% 52.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13888-13895 1 0.00% 52.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14080-14087 64 0.13% 52.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14336-14343 368 0.75% 53.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14848-14855 90 0.18% 53.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15104-15111 84 0.17% 53.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15367 265 0.54% 54.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15616-15623 64 0.13% 54.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16128-16135 70 0.14% 54.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16391 644 1.32% 55.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16640-16647 70 0.14% 55.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17152-17159 65 0.13% 56.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17408-17415 266 0.55% 56.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17664-17671 82 0.17% 56.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17920-17927 88 0.18% 56.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17984-17991 1 0.00% 56.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18176-18183 127 0.26% 57.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18432-18439 370 0.76% 57.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18688-18695 64 0.13% 58.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18944-18951 65 0.13% 58.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19200-19207 69 0.14% 58.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19456-19463 339 0.70% 59.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19712-19719 125 0.26% 59.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19904-19911 1 0.00% 59.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19968-19975 64 0.13% 59.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20224-20231 70 0.14% 59.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20480-20487 325 0.67% 60.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20736-20743 182 0.37% 60.64% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20992-20999 30 0.06% 60.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21248-21255 127 0.26% 60.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21312-21319 1 0.00% 60.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21504-21511 256 0.53% 61.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21632-21639 1 0.00% 61.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21760-21767 65 0.13% 61.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22016-22023 64 0.13% 61.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22272-22279 65 0.13% 61.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22528-22535 320 0.66% 62.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23040-23047 66 0.14% 62.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23552-23559 292 0.60% 63.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23808-23815 1 0.00% 63.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24064-24071 129 0.26% 63.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24384-24391 1 0.00% 63.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24576-24583 538 1.10% 64.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25088-25095 129 0.26% 64.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25344-25351 1 0.00% 64.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25600-25607 292 0.60% 65.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26112-26119 65 0.13% 65.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26624-26631 320 0.66% 66.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26880-26887 65 0.13% 66.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27136-27143 64 0.13% 66.58% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27392-27399 64 0.13% 66.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27648-27655 257 0.53% 67.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27904-27911 128 0.26% 67.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28032-28039 1 0.00% 67.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28160-28167 31 0.06% 67.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28416-28423 182 0.37% 67.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28672-28679 324 0.66% 68.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28928-28935 69 0.14% 68.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29184-29191 64 0.13% 68.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29440-29447 126 0.26% 69.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29696-29703 341 0.70% 69.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29952-29959 69 0.14% 69.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30208-30215 64 0.13% 70.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30464-30471 64 0.13% 70.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30656-30663 1 0.00% 70.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30720-30727 368 0.75% 70.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30976-30983 128 0.26% 71.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31104-31111 1 0.00% 71.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31232-31239 88 0.18% 71.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31488-31495 82 0.17% 71.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31552-31559 1 0.00% 71.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31744-31751 266 0.55% 72.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32000-32007 64 0.13% 72.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32512-32519 69 0.14% 72.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32768-32775 642 1.32% 73.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33024-33031 69 0.14% 73.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33280-33287 1 0.00% 73.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33536-33543 64 0.13% 74.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33792-33799 265 0.54% 74.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33984-33991 1 0.00% 74.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34048-34055 82 0.17% 74.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34240-34247 1 0.00% 74.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34304-34311 88 0.18% 74.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34432-34439 1 0.00% 74.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34816-34823 367 0.75% 75.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34880-34887 1 0.00% 75.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35328-35335 64 0.13% 76.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35456-35463 1 0.00% 76.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35584-35591 69 0.14% 76.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35840-35847 341 0.70% 77.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36096-36103 126 0.26% 77.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36352-36359 64 0.13% 77.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36608-36615 69 0.14% 77.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36864-36871 323 0.66% 78.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37120-37127 182 0.37% 78.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37376-37383 31 0.06% 78.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37504-37511 1 0.00% 78.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37632-37639 129 0.26% 78.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37888-37895 256 0.53% 79.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38144-38151 64 0.13% 79.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38400-38407 64 0.13% 79.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::38912-38919 320 0.66% 80.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39936-39943 292 0.60% 81.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40448-40455 129 0.26% 81.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40960-40967 537 1.10% 82.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41152-41159 1 0.00% 82.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41472-41479 129 0.26% 82.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41984-41991 293 0.60% 83.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42496-42503 66 0.14% 83.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43008-43015 320 0.66% 84.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43264-43271 65 0.13% 84.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43520-43527 65 0.13% 84.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43776-43783 64 0.13% 84.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43904-43911 1 0.00% 84.67% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44032-44039 255 0.52% 85.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44224-44231 2 0.00% 85.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44288-44295 127 0.26% 85.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44544-44551 30 0.06% 85.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44800-44807 181 0.37% 85.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45056-45063 323 0.66% 86.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45312-45319 69 0.14% 86.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45568-45575 64 0.13% 86.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::45824-45831 125 0.26% 87.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46080-46087 338 0.69% 87.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46336-46343 70 0.14% 87.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46592-46599 65 0.13% 88.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47104-47111 369 0.76% 88.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47360-47367 127 0.26% 89.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47552-47559 1 0.00% 89.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47616-47623 90 0.18% 89.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47872-47879 82 0.17% 89.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48128-48135 266 0.55% 90.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48896-48903 69 0.14% 90.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48960-48967 2 0.00% 90.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49152-49159 4685 9.61% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 48746 # Bytes accessed per row activation
|
|
system.physmem.totQLat 326451020750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 407972275750 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 67393460000 # Total ticks spent in databus transfers
|
|
system.physmem.totBankLat 14127795000 # Total ticks spent accessing banks
|
|
system.physmem.avgQLat 24219.78 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBankLat 1048.16 # Average bank access latency per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 30267.94 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 358.88 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 45.68 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 2.81 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 0.38 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 13435238 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 39389 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 88.15 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 172541.07 # Average gap between requests
|
|
system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined
|
|
system.physmem.prechargeAllPercent 0.88 # Percentage of time for which DRAM has all the banks in precharge state
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.throughput 55671057 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 13813895 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 13813895 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 432143 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 432143 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 17007 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 2353 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 2353 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 27827 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 27827 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731520 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951111 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 1682851 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26886592 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 26886592 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 28569443 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735400 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5070524 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.l2c.mem_side::total 5806364 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107546368 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 107546368 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 113352732 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 133814850 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 416796500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 205000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer6.occupancy 14608293500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer6.utilization 0.6 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 1594356888 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 30359701500 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.l2c.tags.replacements 63223 # number of replacements
|
|
system.l2c.tags.tagsinuse 50383.450720 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 1749716 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 128619 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 13.603869 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 2375590593500 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 36838.052028 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 5233.374732 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 3836.748090 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 504.839969 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 688.402361 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.761256 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 1676.159647 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 1594.119177 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.562104 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.079855 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.058544 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.007703 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.010504 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000164 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.025576 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.024324 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.768790 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 65391 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 6483 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 55892 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.997787 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 17682479 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 17682479 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 8678 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 3134 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 467928 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 176815 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 2613 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 1177 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 128266 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 64331 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.dtb.walker 18618 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.itb.walker 4179 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 283323 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 132022 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1291084 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 597612 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 597612 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 5 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu2.data 12 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 61918 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 18367 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu2.data 33347 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 113632 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 8678 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 3134 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 467928 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 238733 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 2613 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 1177 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 128266 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 82698 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.dtb.walker 18618 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.itb.walker 4179 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 283323 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 165369 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1404716 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 8678 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 3134 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 467928 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 238733 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 2613 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 1177 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 128266 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 82698 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.dtb.walker 18618 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.itb.walker 4179 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 283323 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 165369 # number of overall hits
|
|
system.l2c.overall_hits::total 1404716 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 7595 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 6472 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 1007 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 1114 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.dtb.walker 11 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 2890 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 2549 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 21642 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 1432 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 464 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 1010 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 2906 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 104665 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 9733 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 18973 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 133371 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 7595 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 111137 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 1007 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 10847 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.dtb.walker 11 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 2890 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 21522 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 155013 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 7595 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 111137 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 1007 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 10847 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.dtb.walker 11 # number of overall misses
|
|
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|
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|
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|
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|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 1359582856 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 2287855129 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 60036000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 685076023 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 687500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 182410250 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 1359582856 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 2287855129 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25078473000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26153900000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 51232373000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 935173509 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8511559500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 9446733009 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26013646509 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34665459500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 60679106009 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007790 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017022 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000590 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010094 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018867 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.005760 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989339 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.988258 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.502044 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.346370 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.362634 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.116217 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007790 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.115955 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000590 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010094 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.115105 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.023252 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007790 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.115955 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000590 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010094 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.115105 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.023252 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59618.669315 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65432.226212 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63139.581170 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66329.165026 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 64078.494908 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62897.824206 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62782.538660 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 62821.627151 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59618.669315 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63158.110353 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63139.581170 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63201.136854 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 63083.660876 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59618.669315 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63158.110353 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63139.581170 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63201.136854 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 63083.660876 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.toL2Bus.throughput 58820773 # Throughput (bytes/s)
|
|
system.toL2Bus.trans_dist::ReadReq 1019834 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 1019833 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 432143 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 432143 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 265318 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 1491 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 1493 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 80420 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 80420 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831638 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419538 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15322 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51904 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 3318402 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26591040 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37381340 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21424 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84972 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.tot_pkt_size::total 64078776 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.data_through_bus 141286926 # Total data (bytes)
|
|
system.toL2Bus.snoop_data_through_bus 98800 # Total snoop data (bytes)
|
|
system.toL2Bus.reqLayer0.occupancy 2177097249 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 1873558443 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 1846163669 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 9980966 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 30796222 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.throughput 48762593 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 13806282 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 13806282 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 2774 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 2774 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3024 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716528 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 731520 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26886592 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::total 26886592 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 27618112 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6048 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 712856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 735400 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107546368 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107546368 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 108281768 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 117209182 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 1512000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 128000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 358766000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 13443296000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 728746000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 36856311500 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 7990923 # DTB read hits
|
|
system.cpu0.dtb.read_misses 6211 # DTB read misses
|
|
system.cpu0.dtb.write_hits 6594140 # DTB write hits
|
|
system.cpu0.dtb.write_misses 1982 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 5674 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 122 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 7997134 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 6596122 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 14585063 # DTB hits
|
|
system.cpu0.dtb.misses 8193 # DTB misses
|
|
system.cpu0.dtb.accesses 14593256 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.inst_hits 32307309 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 3464 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2638 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 32310773 # ITB inst accesses
|
|
system.cpu0.itb.hits 32307309 # DTB hits
|
|
system.cpu0.itb.misses 3464 # DTB misses
|
|
system.cpu0.itb.accesses 32310773 # DTB accesses
|
|
system.cpu0.numCycles 113705948 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 31835702 # Number of instructions committed
|
|
system.cpu0.committedOps 42002663 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 37391372 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 1198329 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 4242666 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 37391372 # number of integer instructions
|
|
system.cpu0.num_fp_insts 4937 # number of float instructions
|
|
system.cpu0.num_int_register_reads 193815032 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 39491762 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 15252645 # number of memory refs
|
|
system.cpu0.num_load_insts 8359351 # Number of load instructions
|
|
system.cpu0.num_store_insts 6893294 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 111019314.623883 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 2686633.376117 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.023628 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.976372 # Percentage of idle cycles
|
|
system.cpu0.Branches 5610345 # Number of branches fetched
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed
|
|
system.cpu0.icache.tags.replacements 891892 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.603893 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 43639057 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 892404 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 48.900562 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 8180676250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.451765 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.618297 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu2.inst 8.533831 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967679 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014879 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.016668 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 45447878 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 45447878 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 31833706 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 8062582 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu2.inst 3742769 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 43639057 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 31833706 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 8062582 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu2.inst 3742769 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 43639057 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 31833706 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 8062582 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu2.inst 3742769 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 43639057 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 476257 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 129542 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu2.inst 310613 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 916412 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 476257 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 129542 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu2.inst 310613 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 916412 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 476257 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 129542 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu2.inst 310613 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 916412 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1750680500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4190164618 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 5940845118 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 1750680500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu2.inst 4190164618 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 5940845118 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 1750680500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu2.inst 4190164618 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 5940845118 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32309963 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 8192124 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu2.inst 4053382 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 44555469 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 32309963 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 8192124 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu2.inst 4053382 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 44555469 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 32309963 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 8192124 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu2.inst 4053382 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 44555469 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014740 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015813 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076631 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.020568 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014740 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015813 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076631 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.020568 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014740 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015813 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076631 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.020568 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13514.385296 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13489.984701 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 6482.722965 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13514.385296 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13489.984701 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 6482.722965 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13514.385296 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13489.984701 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 6482.722965 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 4056 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.588832 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24002 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 24002 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu2.inst 24002 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 24002 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu2.inst 24002 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 24002 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129542 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 286611 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 416153 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 129542 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu2.inst 286611 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 416153 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 129542 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu2.inst 286611 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 416153 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1491204500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3408089041 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4899293541 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1491204500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3408089041 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 4899293541 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1491204500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3408089041 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 4899293541 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015813 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070709 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009340 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015813 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070709 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.009340 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015813 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070709 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.009340 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11511.359250 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11890.991766 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11772.818028 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11511.359250 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11890.991766 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11772.818028 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11511.359250 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11890.991766 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11772.818028 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.tags.replacements 629794 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.997118 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 23221016 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 630306 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 36.840861 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.062624 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.150626 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.783867 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970825 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015919 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013250 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 98822314 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 98822314 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6860309 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 1818197 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu2.data 4643556 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 13322062 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 5962720 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 1310571 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu2.data 2137098 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 9410389 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131686 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33079 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73392 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 238157 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138128 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34832 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74432 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 247392 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 12823029 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 3128768 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu2.data 6780654 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 22732451 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 12823029 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 3128768 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu2.data 6780654 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 22732451 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 176845 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 63692 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu2.data 271624 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 512161 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 168028 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 28569 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu2.data 609317 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 805914 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6442 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1753 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3730 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 11925 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 344873 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 92261 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu2.data 880941 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1318075 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 344873 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 92261 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu2.data 880941 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1318075 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 907950750 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3924341569 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 4832292319 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1018206487 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 23272443628 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 24290650115 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 23011750 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 49882999 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 72894749 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 1926157237 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu2.data 27196785197 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 29122942434 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 1926157237 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu2.data 27196785197 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 29122942434 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7037154 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1881889 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4915180 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 13834223 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 6130748 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1339140 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2746415 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 10216303 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138128 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34832 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77122 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 250082 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138128 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34832 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74434 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 247394 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 13167902 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 3221029 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu2.data 7661595 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 24050526 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 13167902 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 3221029 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu2.data 7661595 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 24050526 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025130 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033845 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055262 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.037021 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027407 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021334 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.221859 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.078885 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046638 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050327 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048365 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047684 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026190 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028643 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114981 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.054804 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026190 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028643 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.114981 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.054804 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14255.334265 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14447.698175 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 9435.104038 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35640.256467 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38194.312038 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30140.499005 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.067884 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13373.458177 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6112.767212 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20877.263817 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30872.425278 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 22095.057136 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20877.263817 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30872.425278 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 22095.057136 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 8107 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 3163 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 889 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 50 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.119235 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 63.260000 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 597612 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 597612 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 140350 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 140350 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556007 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 556007 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 401 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 401 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu2.data 696357 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 696357 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu2.data 696357 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 696357 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63692 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131274 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 194966 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28569 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53310 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 81879 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1753 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3329 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5082 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 92261 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu2.data 184584 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 276845 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 92261 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 184584 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 276845 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 780369250 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1701870584 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2482239834 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 958496513 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1869248236 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2827744749 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19505250 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38414501 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57919751 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1738865763 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3571118820 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 5309984583 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1738865763 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3571118820 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 5309984583 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27398396000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28553530500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55951926500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442155991 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13334829583 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14776985574 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28840551991 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41888360083 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70728912074 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033845 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026708 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014093 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021334 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019411 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008015 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050327 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043165 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020321 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028643 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.011511 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028643 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.011511 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12252.233405 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12964.262413 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12731.654924 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33550.229725 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35063.744813 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34535.653208 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11126.782658 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11539.351457 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11397.038764 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18847.245998 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19346.849239 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19180.352121 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18847.245998 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19346.849239 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19180.352121 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 2095173 # DTB read hits
|
|
system.cpu1.dtb.read_misses 2089 # DTB read misses
|
|
system.cpu1.dtb.write_hits 1414657 # DTB write hits
|
|
system.cpu1.dtb.write_misses 374 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 220 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 13 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1771 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 38 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 2097262 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 1415031 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 3509830 # DTB hits
|
|
system.cpu1.dtb.misses 2463 # DTB misses
|
|
system.cpu1.dtb.accesses 3512293 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.inst_hits 8192124 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 1194 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 554 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 220 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 13 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 949 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 8193318 # ITB inst accesses
|
|
system.cpu1.itb.hits 8192124 # DTB hits
|
|
system.cpu1.itb.misses 1194 # DTB misses
|
|
system.cpu1.itb.accesses 8193318 # DTB accesses
|
|
system.cpu1.numCycles 581420474 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 7979382 # Number of instructions committed
|
|
system.cpu1.committedOps 10120569 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 9091581 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 1987 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 304296 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 1113753 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 9091581 # number of integer instructions
|
|
system.cpu1.num_fp_insts 1987 # number of float instructions
|
|
system.cpu1.num_int_register_reads 53006739 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 9888017 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 1409 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 3676771 # number of memory refs
|
|
system.cpu1.num_load_insts 2188618 # Number of load instructions
|
|
system.cpu1.num_store_insts 1488153 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 545340562.414449 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 36079911.585551 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.062055 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.937945 # Percentage of idle cycles
|
|
system.cpu1.Branches 1446360 # Number of branches fetched
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu2.branchPred.lookups 4789734 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 3907352 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 223904 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 3178605 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 2529099 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 79.566319 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 413607 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 21727 # Number of incorrect RAS predictions.
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu2.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dtb.read_hits 10928591 # DTB read hits
|
|
system.cpu2.dtb.read_misses 22863 # DTB read misses
|
|
system.cpu2.dtb.write_hits 3355192 # DTB write hits
|
|
system.cpu2.dtb.write_misses 6501 # DTB write misses
|
|
system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed
|
|
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dtb.flush_tlb_mva_asid 538 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dtb.flush_entries 2326 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dtb.align_faults 747 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dtb.prefetch_faults 160 # Number of TLB faults due to prefetch
|
|
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dtb.perms_faults 464 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dtb.read_accesses 10951454 # DTB read accesses
|
|
system.cpu2.dtb.write_accesses 3361693 # DTB write accesses
|
|
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dtb.hits 14283783 # DTB hits
|
|
system.cpu2.dtb.misses 29364 # DTB misses
|
|
system.cpu2.dtb.accesses 14313147 # DTB accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu2.itb.inst_hits 4054873 # ITB inst hits
|
|
system.cpu2.itb.inst_misses 4512 # ITB inst misses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed
|
|
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.itb.flush_tlb_mva_asid 538 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
|
|
system.cpu2.itb.flush_entries 1691 # Number of entries that have been flushed from TLB
|
|
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.itb.perms_faults 1038 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.inst_accesses 4059385 # ITB inst accesses
|
|
system.cpu2.itb.hits 4054873 # DTB hits
|
|
system.cpu2.itb.misses 4512 # DTB misses
|
|
system.cpu2.itb.accesses 4059385 # DTB accesses
|
|
system.cpu2.numCycles 88337048 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 9388767 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 32522302 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 4789734 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 2942706 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 6862489 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 1760464 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.TlbCycles 49990 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu2.fetch.BlockedCycles 19168441 # Number of cycles fetch has spent blocked
|
|
system.cpu2.fetch.MiscStallCycles 508 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.PendingDrainCycles 916 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu2.fetch.PendingTrapStallCycles 33389 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.PendingQuiesceStallCycles 724944 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu2.fetch.IcacheWaitRetryStallCycles 411 # Number of stall cycles due to full MSHR
|
|
system.cpu2.fetch.CacheLines 4053387 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 290500 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 37439208 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.044253 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.431681 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 30581596 81.68% 81.68% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 385766 1.03% 82.71% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 516570 1.38% 84.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 819401 2.19% 86.28% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 630355 1.68% 87.97% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 341667 0.91% 88.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 1045652 2.79% 91.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 230362 0.62% 92.29% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 2887839 7.71% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 37439208 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.054221 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 0.368162 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 10012366 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 19744012 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 6199418 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 325352 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 1157163 # Number of cycles decode is squashing
|
|
system.cpu2.decode.BranchResolved 610165 # Number of times decode resolved a branch
|
|
system.cpu2.decode.BranchMispred 53442 # Number of times decode detected a branch misprediction
|
|
system.cpu2.decode.DecodedInsts 36995280 # Number of instructions handled by decode
|
|
system.cpu2.decode.SquashedInsts 180745 # Number of squashed instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 1157163 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 10561732 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 6812365 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 11427981 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 5960297 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 1518769 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 34903210 # Number of instructions processed by rename
|
|
system.cpu2.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full
|
|
system.cpu2.rename.IQFullEvents 326244 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LSQFullEvents 883069 # Number of times rename has blocked due to LSQ full
|
|
system.cpu2.rename.FullRegisterEvents 119 # Number of times there has been no free registers
|
|
system.cpu2.rename.RenamedOperands 37436972 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 161085942 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 148506742 # Number of integer rename lookups
|
|
system.cpu2.rename.fp_rename_lookups 3418 # Number of floating rename lookups
|
|
system.cpu2.rename.CommittedMaps 26572380 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 10864591 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 285670 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 261929 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 3326002 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 6631520 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 3908381 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 522508 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 782143 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 32221978 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 504989 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 34786596 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 55958 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 7182504 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 19112764 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 148353 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 37439208 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 0.929149 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.590514 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 24741126 66.08% 66.08% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 3984374 10.64% 76.73% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 2311240 6.17% 82.90% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 1973818 5.27% 88.17% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 2779235 7.42% 95.59% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 969976 2.59% 98.19% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 499460 1.33% 99.52% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 145124 0.39% 99.91% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 34855 0.09% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 37439208 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 19410 1.27% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 1 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 1392857 91.45% 92.72% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 110885 7.28% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 8329 0.02% 0.02% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 19813633 56.96% 56.98% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 28024 0.08% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 386 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 11412307 32.81% 89.87% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 3523902 10.13% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 34786596 # Type of FU issued
|
|
system.cpu2.iq.rate 0.393794 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 1523153 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.043786 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 108613127 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 39914727 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 28091280 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 7607 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 3993 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 3398 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 36297355 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 4065 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 206023 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 1534437 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 2089 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 9566 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 563640 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 5283023 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 345372 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 1157163 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 5185391 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 88081 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 32809694 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 61016 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 6631520 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 3908381 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 362677 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 29698 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 2464 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 9566 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 107529 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 89869 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 197398 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 33871170 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 11141481 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 915426 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 82727 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 14631897 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 3767155 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 3490416 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 0.383431 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 33470061 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 28094678 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 16123172 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 29138246 # num instructions consuming a value
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.wb_rate 0.318040 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.553334 # average fanout of values written-back
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.commit.commitSquashedInsts 7139947 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 356636 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 171258 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 36281839 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 0.700541 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 1.737980 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 27358624 75.41% 75.41% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 4439139 12.24% 87.64% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 1255970 3.46% 91.10% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 641270 1.77% 92.87% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 512644 1.41% 94.28% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 317320 0.87% 95.16% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 419851 1.16% 96.31% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 310411 0.86% 97.17% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 1026610 2.83% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 36281839 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 20568992 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 25416928 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 8441824 # Number of memory references committed
|
|
system.cpu2.commit.loads 5097083 # Number of loads committed
|
|
system.cpu2.commit.membars 94345 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 3244670 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 3331 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 22669662 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 295973 # Number of function calls committed.
|
|
system.cpu2.commit.bw_lim_events 1026610 # number cycles where commit BW limit reached
|
|
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu2.rob.rob_reads 67290844 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 66314967 # The number of ROB writes
|
|
system.cpu2.timesIdled 359753 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 50897840 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 3553970695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 20513640 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 25361576 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.committedInsts_total 20513640 # Number of Instructions Simulated
|
|
system.cpu2.cpi 4.306259 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 4.306259 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 0.232220 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 0.232220 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 157179181 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 29907517 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_reads 46919 # number of floating regfile reads
|
|
system.cpu2.fp_regfile_writes 45194 # number of floating regfile writes
|
|
system.cpu2.misc_regfile_reads 66774204 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 297147 # number of misc regfile writes
|
|
system.iocache.tags.replacements 0 # number of replacements
|
|
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 0 # Number of data accesses
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347815916500 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1347815916500 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347815916500 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1347815916500 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|