e097c4fb18
Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit.
523 lines
18 KiB
C++
523 lines
18 KiB
C++
/*
|
|
* Copyright (c) 2010 ARM Limited
|
|
* All rights reserved
|
|
*
|
|
* The license below extends only to copyright in the software and shall
|
|
* not be construed as granting a license to any other intellectual
|
|
* property including but not limited to intellectual property relating
|
|
* to a hardware implementation of the functionality of the software
|
|
* licensed hereunder. You may use the software subject to the license
|
|
* terms below provided that you ensure that this notice is replicated
|
|
* unmodified and in its entirety in all distributions of the software,
|
|
* modified or unmodified, in source code or in binary form.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*
|
|
* Authors: Gabe Black
|
|
* Ali Saidi
|
|
*/
|
|
|
|
#include "arch/arm/isa.hh"
|
|
#include "debug/Arm.hh"
|
|
#include "debug/MiscRegs.hh"
|
|
#include "sim/faults.hh"
|
|
#include "sim/stat_control.hh"
|
|
#include "sim/system.hh"
|
|
|
|
namespace ArmISA
|
|
{
|
|
|
|
void
|
|
ISA::clear()
|
|
{
|
|
SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
|
|
uint32_t midr = miscRegs[MISCREG_MIDR];
|
|
memset(miscRegs, 0, sizeof(miscRegs));
|
|
CPSR cpsr = 0;
|
|
cpsr.mode = MODE_USER;
|
|
miscRegs[MISCREG_CPSR] = cpsr;
|
|
updateRegMap(cpsr);
|
|
|
|
SCTLR sctlr = 0;
|
|
sctlr.te = (bool)sctlr_rst.te;
|
|
sctlr.nmfi = (bool)sctlr_rst.nmfi;
|
|
sctlr.v = (bool)sctlr_rst.v;
|
|
sctlr.u = 1;
|
|
sctlr.xp = 1;
|
|
sctlr.rao2 = 1;
|
|
sctlr.rao3 = 1;
|
|
sctlr.rao4 = 1;
|
|
miscRegs[MISCREG_SCTLR] = sctlr;
|
|
miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
|
|
|
|
// Preserve MIDR accross reset
|
|
miscRegs[MISCREG_MIDR] = midr;
|
|
|
|
/* Start with an event in the mailbox */
|
|
miscRegs[MISCREG_SEV_MAILBOX] = 1;
|
|
|
|
// Separate Instruction and Data TLBs.
|
|
miscRegs[MISCREG_TLBTR] = 1;
|
|
|
|
MVFR0 mvfr0 = 0;
|
|
mvfr0.advSimdRegisters = 2;
|
|
mvfr0.singlePrecision = 2;
|
|
mvfr0.doublePrecision = 2;
|
|
mvfr0.vfpExceptionTrapping = 0;
|
|
mvfr0.divide = 1;
|
|
mvfr0.squareRoot = 1;
|
|
mvfr0.shortVectors = 1;
|
|
mvfr0.roundingModes = 1;
|
|
miscRegs[MISCREG_MVFR0] = mvfr0;
|
|
|
|
MVFR1 mvfr1 = 0;
|
|
mvfr1.flushToZero = 1;
|
|
mvfr1.defaultNaN = 1;
|
|
mvfr1.advSimdLoadStore = 1;
|
|
mvfr1.advSimdInteger = 1;
|
|
mvfr1.advSimdSinglePrecision = 1;
|
|
mvfr1.advSimdHalfPrecision = 1;
|
|
mvfr1.vfpHalfPrecision = 1;
|
|
miscRegs[MISCREG_MVFR1] = mvfr1;
|
|
|
|
miscRegs[MISCREG_MPIDR] = 0;
|
|
|
|
// Reset values of PRRR and NMRR are implementation dependent
|
|
|
|
miscRegs[MISCREG_PRRR] =
|
|
(1 << 19) | // 19
|
|
(0 << 18) | // 18
|
|
(0 << 17) | // 17
|
|
(1 << 16) | // 16
|
|
(2 << 14) | // 15:14
|
|
(0 << 12) | // 13:12
|
|
(2 << 10) | // 11:10
|
|
(2 << 8) | // 9:8
|
|
(2 << 6) | // 7:6
|
|
(2 << 4) | // 5:4
|
|
(1 << 2) | // 3:2
|
|
0; // 1:0
|
|
miscRegs[MISCREG_NMRR] =
|
|
(1 << 30) | // 31:30
|
|
(0 << 26) | // 27:26
|
|
(0 << 24) | // 25:24
|
|
(3 << 22) | // 23:22
|
|
(2 << 20) | // 21:20
|
|
(0 << 18) | // 19:18
|
|
(0 << 16) | // 17:16
|
|
(1 << 14) | // 15:14
|
|
(0 << 12) | // 13:12
|
|
(2 << 10) | // 11:10
|
|
(0 << 8) | // 9:8
|
|
(3 << 6) | // 7:6
|
|
(2 << 4) | // 5:4
|
|
(0 << 2) | // 3:2
|
|
0; // 1:0
|
|
|
|
miscRegs[MISCREG_CPACR] = 0;
|
|
miscRegs[MISCREG_FPSID] = 0x410430A0;
|
|
|
|
// See section B4.1.84 of ARM ARM
|
|
// All values are latest for ARMv7-A profile
|
|
miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
|
|
miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
|
|
miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
|
|
miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
|
|
miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
|
|
miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
|
|
|
|
//XXX We need to initialize the rest of the state.
|
|
}
|
|
|
|
MiscReg
|
|
ISA::readMiscRegNoEffect(int misc_reg)
|
|
{
|
|
assert(misc_reg < NumMiscRegs);
|
|
|
|
int flat_idx;
|
|
if (misc_reg == MISCREG_SPSR)
|
|
flat_idx = flattenMiscIndex(misc_reg);
|
|
else
|
|
flat_idx = misc_reg;
|
|
MiscReg val = miscRegs[flat_idx];
|
|
|
|
DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
|
|
misc_reg, flat_idx, val);
|
|
return val;
|
|
}
|
|
|
|
|
|
MiscReg
|
|
ISA::readMiscReg(int misc_reg, ThreadContext *tc)
|
|
{
|
|
if (misc_reg == MISCREG_CPSR) {
|
|
CPSR cpsr = miscRegs[misc_reg];
|
|
PCState pc = tc->pcState();
|
|
cpsr.j = pc.jazelle() ? 1 : 0;
|
|
cpsr.t = pc.thumb() ? 1 : 0;
|
|
return cpsr;
|
|
}
|
|
if (misc_reg >= MISCREG_CP15_UNIMP_START)
|
|
panic("Unimplemented CP15 register %s read.\n",
|
|
miscRegName[misc_reg]);
|
|
|
|
switch (misc_reg) {
|
|
case MISCREG_MPIDR:
|
|
return tc->cpuId();
|
|
break;
|
|
case MISCREG_ID_MMFR3:
|
|
return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
|
|
// BP Maint | Cache Maint Set/way | Cache Maint MVA
|
|
case MISCREG_CLIDR:
|
|
warn_once("The clidr register always reports 0 caches.\n");
|
|
break;
|
|
case MISCREG_CCSIDR:
|
|
warn_once("The ccsidr register isn't implemented and "
|
|
"always reads as 0.\n");
|
|
break;
|
|
case MISCREG_ID_PFR0:
|
|
warn("Returning thumbEE disabled for now since we don't support CP14"
|
|
"config registers and jumping to ThumbEE vectors\n");
|
|
return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
|
|
case MISCREG_ID_PFR1:
|
|
warn("reading unimplmented register ID_PFR1");
|
|
return 0;
|
|
case MISCREG_ID_MMFR0:
|
|
return 0x03; //VMSAz7
|
|
case MISCREG_CTR:
|
|
return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
|
|
case MISCREG_ACTLR:
|
|
warn("Not doing anything for miscreg ACTLR\n");
|
|
break;
|
|
case MISCREG_PMCR:
|
|
case MISCREG_PMCCNTR:
|
|
case MISCREG_PMSELR:
|
|
warn("Not doing anything for read to miscreg %s\n",
|
|
miscRegName[misc_reg]);
|
|
break;
|
|
case MISCREG_CPSR_Q:
|
|
panic("shouldn't be reading this register seperately\n");
|
|
case MISCREG_FPSCR_QC:
|
|
return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
|
|
case MISCREG_FPSCR_EXC:
|
|
return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
|
|
}
|
|
return readMiscRegNoEffect(misc_reg);
|
|
}
|
|
|
|
void
|
|
ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
|
|
{
|
|
assert(misc_reg < NumMiscRegs);
|
|
|
|
int flat_idx;
|
|
if (misc_reg == MISCREG_SPSR)
|
|
flat_idx = flattenMiscIndex(misc_reg);
|
|
else
|
|
flat_idx = misc_reg;
|
|
miscRegs[flat_idx] = val;
|
|
|
|
DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
|
|
flat_idx, val);
|
|
}
|
|
|
|
void
|
|
ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
|
|
{
|
|
|
|
MiscReg newVal = val;
|
|
int x;
|
|
System *sys;
|
|
ThreadContext *oc;
|
|
|
|
if (misc_reg == MISCREG_CPSR) {
|
|
updateRegMap(val);
|
|
|
|
|
|
CPSR old_cpsr = miscRegs[MISCREG_CPSR];
|
|
int old_mode = old_cpsr.mode;
|
|
CPSR cpsr = val;
|
|
if (old_mode != cpsr.mode) {
|
|
tc->getITBPtr()->invalidateMiscReg();
|
|
tc->getDTBPtr()->invalidateMiscReg();
|
|
}
|
|
|
|
DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
|
|
miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
|
|
PCState pc = tc->pcState();
|
|
pc.nextThumb(cpsr.t);
|
|
pc.nextJazelle(cpsr.j);
|
|
tc->pcState(pc);
|
|
} else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
|
|
misc_reg < MISCREG_CP15_END) {
|
|
panic("Unimplemented CP15 register %s wrote with %#x.\n",
|
|
miscRegName[misc_reg], val);
|
|
} else {
|
|
switch (misc_reg) {
|
|
case MISCREG_CPACR:
|
|
{
|
|
|
|
const uint32_t ones = (uint32_t)(-1);
|
|
CPACR cpacrMask = 0;
|
|
// Only cp10, cp11, and ase are implemented, nothing else should
|
|
// be writable
|
|
cpacrMask.cp10 = ones;
|
|
cpacrMask.cp11 = ones;
|
|
cpacrMask.asedis = ones;
|
|
newVal &= cpacrMask;
|
|
DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
|
|
miscRegName[misc_reg], newVal);
|
|
}
|
|
break;
|
|
case MISCREG_CSSELR:
|
|
warn_once("The csselr register isn't implemented.\n");
|
|
return;
|
|
case MISCREG_FPSCR:
|
|
{
|
|
const uint32_t ones = (uint32_t)(-1);
|
|
FPSCR fpscrMask = 0;
|
|
fpscrMask.ioc = ones;
|
|
fpscrMask.dzc = ones;
|
|
fpscrMask.ofc = ones;
|
|
fpscrMask.ufc = ones;
|
|
fpscrMask.ixc = ones;
|
|
fpscrMask.idc = ones;
|
|
fpscrMask.len = ones;
|
|
fpscrMask.stride = ones;
|
|
fpscrMask.rMode = ones;
|
|
fpscrMask.fz = ones;
|
|
fpscrMask.dn = ones;
|
|
fpscrMask.ahp = ones;
|
|
fpscrMask.qc = ones;
|
|
fpscrMask.v = ones;
|
|
fpscrMask.c = ones;
|
|
fpscrMask.z = ones;
|
|
fpscrMask.n = ones;
|
|
newVal = (newVal & (uint32_t)fpscrMask) |
|
|
(miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
|
|
}
|
|
break;
|
|
case MISCREG_CPSR_Q:
|
|
{
|
|
assert(!(newVal & ~CpsrMaskQ));
|
|
newVal = miscRegs[MISCREG_CPSR] | newVal;
|
|
misc_reg = MISCREG_CPSR;
|
|
}
|
|
break;
|
|
case MISCREG_FPSCR_QC:
|
|
{
|
|
newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
|
|
misc_reg = MISCREG_FPSCR;
|
|
}
|
|
break;
|
|
case MISCREG_FPSCR_EXC:
|
|
{
|
|
newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
|
|
misc_reg = MISCREG_FPSCR;
|
|
}
|
|
break;
|
|
case MISCREG_FPEXC:
|
|
{
|
|
// vfpv3 architecture, section B.6.1 of DDI04068
|
|
// bit 29 - valid only if fpexc[31] is 0
|
|
const uint32_t fpexcMask = 0x60000000;
|
|
newVal = (newVal & fpexcMask) |
|
|
(miscRegs[MISCREG_FPEXC] & ~fpexcMask);
|
|
}
|
|
break;
|
|
case MISCREG_SCTLR:
|
|
{
|
|
DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
|
|
SCTLR sctlr = miscRegs[MISCREG_SCTLR];
|
|
SCTLR new_sctlr = newVal;
|
|
new_sctlr.nmfi = (bool)sctlr.nmfi;
|
|
miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
|
|
tc->getITBPtr()->invalidateMiscReg();
|
|
tc->getDTBPtr()->invalidateMiscReg();
|
|
return;
|
|
}
|
|
case MISCREG_TLBTR:
|
|
case MISCREG_MVFR0:
|
|
case MISCREG_MVFR1:
|
|
case MISCREG_MPIDR:
|
|
case MISCREG_FPSID:
|
|
return;
|
|
case MISCREG_TLBIALLIS:
|
|
case MISCREG_TLBIALL:
|
|
sys = tc->getSystemPtr();
|
|
for (x = 0; x < sys->numContexts(); x++) {
|
|
oc = sys->getThreadContext(x);
|
|
assert(oc->getITBPtr() && oc->getDTBPtr());
|
|
oc->getITBPtr()->flushAll();
|
|
oc->getDTBPtr()->flushAll();
|
|
}
|
|
return;
|
|
case MISCREG_ITLBIALL:
|
|
tc->getITBPtr()->flushAll();
|
|
return;
|
|
case MISCREG_DTLBIALL:
|
|
tc->getDTBPtr()->flushAll();
|
|
return;
|
|
case MISCREG_TLBIMVAIS:
|
|
case MISCREG_TLBIMVA:
|
|
sys = tc->getSystemPtr();
|
|
for (x = 0; x < sys->numContexts(); x++) {
|
|
oc = sys->getThreadContext(x);
|
|
assert(oc->getITBPtr() && oc->getDTBPtr());
|
|
oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
|
bits(newVal, 7,0));
|
|
oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
|
bits(newVal, 7,0));
|
|
}
|
|
return;
|
|
case MISCREG_TLBIASIDIS:
|
|
case MISCREG_TLBIASID:
|
|
sys = tc->getSystemPtr();
|
|
for (x = 0; x < sys->numContexts(); x++) {
|
|
oc = sys->getThreadContext(x);
|
|
assert(oc->getITBPtr() && oc->getDTBPtr());
|
|
oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
|
|
oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
|
|
}
|
|
return;
|
|
case MISCREG_TLBIMVAAIS:
|
|
case MISCREG_TLBIMVAA:
|
|
sys = tc->getSystemPtr();
|
|
for (x = 0; x < sys->numContexts(); x++) {
|
|
oc = sys->getThreadContext(x);
|
|
assert(oc->getITBPtr() && oc->getDTBPtr());
|
|
oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
|
|
oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
|
|
}
|
|
return;
|
|
case MISCREG_ITLBIMVA:
|
|
tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
|
bits(newVal, 7,0));
|
|
return;
|
|
case MISCREG_DTLBIMVA:
|
|
tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
|
bits(newVal, 7,0));
|
|
return;
|
|
case MISCREG_ITLBIASID:
|
|
tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
|
|
return;
|
|
case MISCREG_DTLBIASID:
|
|
tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
|
|
return;
|
|
case MISCREG_ACTLR:
|
|
warn("Not doing anything for write of miscreg ACTLR\n");
|
|
break;
|
|
case MISCREG_PMCR:
|
|
{
|
|
// Performance counters not implemented. Instead, interpret
|
|
// a reset command to this register to reset the simulator
|
|
// statistics.
|
|
// PMCR_E | PMCR_P | PMCR_C
|
|
const int ResetAndEnableCounters = 0x7;
|
|
if (newVal == ResetAndEnableCounters) {
|
|
inform("Resetting all simobject stats\n");
|
|
Stats::schedStatEvent(false, true);
|
|
break;
|
|
}
|
|
}
|
|
case MISCREG_PMCCNTR:
|
|
case MISCREG_PMSELR:
|
|
warn("Not doing anything for write to miscreg %s\n",
|
|
miscRegName[misc_reg]);
|
|
break;
|
|
case MISCREG_V2PCWPR:
|
|
case MISCREG_V2PCWPW:
|
|
case MISCREG_V2PCWUR:
|
|
case MISCREG_V2PCWUW:
|
|
case MISCREG_V2POWPR:
|
|
case MISCREG_V2POWPW:
|
|
case MISCREG_V2POWUR:
|
|
case MISCREG_V2POWUW:
|
|
{
|
|
RequestPtr req = new Request;
|
|
unsigned flags;
|
|
BaseTLB::Mode mode;
|
|
Fault fault;
|
|
switch(misc_reg) {
|
|
case MISCREG_V2PCWPR:
|
|
flags = TLB::MustBeOne;
|
|
mode = BaseTLB::Read;
|
|
break;
|
|
case MISCREG_V2PCWPW:
|
|
flags = TLB::MustBeOne;
|
|
mode = BaseTLB::Write;
|
|
break;
|
|
case MISCREG_V2PCWUR:
|
|
flags = TLB::MustBeOne | TLB::UserMode;
|
|
mode = BaseTLB::Read;
|
|
break;
|
|
case MISCREG_V2PCWUW:
|
|
flags = TLB::MustBeOne | TLB::UserMode;
|
|
mode = BaseTLB::Write;
|
|
break;
|
|
default:
|
|
panic("Security Extensions not implemented!");
|
|
}
|
|
warn("Translating via MISCREG in atomic mode! Fix Me!\n");
|
|
req->setVirt(0, val, 1, flags, tc->pcState().pc());
|
|
fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
|
|
if (fault == NoFault) {
|
|
miscRegs[MISCREG_PAR] =
|
|
(req->getPaddr() & 0xfffff000) |
|
|
(tc->getDTBPtr()->getAttr() );
|
|
DPRINTF(MiscRegs,
|
|
"MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
|
|
val, miscRegs[MISCREG_PAR]);
|
|
}
|
|
else {
|
|
// Set fault bit and FSR
|
|
FSR fsr = miscRegs[MISCREG_DFSR];
|
|
miscRegs[MISCREG_PAR] =
|
|
(fsr.ext << 6) |
|
|
(fsr.fsHigh << 5) |
|
|
(fsr.fsLow << 1) |
|
|
0x1; // F bit
|
|
}
|
|
return;
|
|
}
|
|
case MISCREG_CONTEXTIDR:
|
|
case MISCREG_PRRR:
|
|
case MISCREG_NMRR:
|
|
case MISCREG_DACR:
|
|
tc->getITBPtr()->invalidateMiscReg();
|
|
tc->getDTBPtr()->invalidateMiscReg();
|
|
break;
|
|
case MISCREG_CPSR_MODE:
|
|
// This miscreg is used by copy*Regs to set the CPSR mode
|
|
// without updating other CPSR variables. It's used to
|
|
// make sure the register map is in such a state that we can
|
|
// see all of the registers for the copy.
|
|
updateRegMap(val);
|
|
return;
|
|
}
|
|
}
|
|
setMiscRegNoEffect(misc_reg, newVal);
|
|
}
|
|
|
|
}
|