62fa781fee
object defined there was renamed Root long ago). SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: base/misc.cc: base/pollevent.cc: base/pollevent.hh: base/stats/events.cc: base/trace.hh: cpu/beta_cpu/fetch_impl.hh: cpu/beta_cpu/full_cpu.cc: cpu/beta_cpu/inst_queue_impl.hh: cpu/pc_event.cc: cpu/static_inst.cc: dev/etherbus.cc: dev/etherdump.cc: dev/etherlink.cc: dev/ide_disk.cc: dev/pcidev.cc: sim/builder.cc: sim/eventq.cc: sim/main.cc: sim/root.cc: sim/stat_control.cc: Rename sim/universe.{cc,hh} to root.{cc,hh}. --HG-- rename : sim/universe.cc => sim/root.cc extra : convert_revision : b8699e81e285253d66da75412e7bb2c251c0389a
221 lines
5.1 KiB
C++
221 lines
5.1 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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// This file will contain default statistics for the simulator that
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// don't really belong to a specific simulator object
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#include <fstream>
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#include <iostream>
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#include <list>
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#include "base/callback.hh"
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#include "base/hostinfo.hh"
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#include "base/statistics.hh"
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#include "base/str.hh"
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#include "base/time.hh"
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#include "base/stats/output.hh"
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#include "cpu/base_cpu.hh"
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#include "sim/eventq.hh"
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#include "sim/sim_object.hh"
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#include "sim/stat_control.hh"
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#include "sim/root.hh"
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using namespace std;
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Stats::Formula hostInstRate;
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Stats::Formula hostTickRate;
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Stats::Value hostMemory;
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Stats::Value hostSeconds;
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Stats::Value simTicks;
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Stats::Value simInsts;
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Stats::Value simFreq;
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Stats::Formula simSeconds;
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namespace Stats {
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Time statTime(true);
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Tick startTick;
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class SimTicksReset : public Callback
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{
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public:
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void process()
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{
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statTime.set();
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startTick = curTick;
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}
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};
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double
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statElapsedTime()
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{
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Time now(true);
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Time elapsed = now - statTime;
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return elapsed();
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}
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Tick
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statElapsedTicks()
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{
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return curTick - startTick;
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}
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SimTicksReset simTicksReset;
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void
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InitSimStats()
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{
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simInsts
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.functor(BaseCPU::numSimulatedInstructions)
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.name("sim_insts")
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.desc("Number of instructions simulated")
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.precision(0)
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.prereq(simInsts)
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;
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simSeconds
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.name("sim_seconds")
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.desc("Number of seconds simulated")
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;
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simFreq
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.scalar(Clock::Frequency)
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.name("sim_freq")
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.desc("Frequency of simulated ticks")
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;
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simTicks
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.functor(statElapsedTicks)
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.name("sim_ticks")
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.desc("Number of ticks simulated")
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;
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hostInstRate
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.name("host_inst_rate")
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.desc("Simulator instruction rate (inst/s)")
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.precision(0)
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.prereq(simInsts)
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;
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hostMemory
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.functor(memUsage)
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.name("host_mem_usage")
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.desc("Number of bytes of host memory used")
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.prereq(hostMemory)
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;
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hostSeconds
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.functor(statElapsedTime)
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.name("host_seconds")
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.desc("Real time elapsed on the host")
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.precision(2)
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;
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hostTickRate
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.name("host_tick_rate")
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.desc("Simulator tick rate (ticks/s)")
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.precision(0)
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;
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simSeconds = simTicks / simFreq;
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hostInstRate = simInsts / hostSeconds;
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hostTickRate = simTicks / hostSeconds;
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registerResetCallback(&simTicksReset);
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}
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class StatEvent : public Event
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{
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protected:
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int flags;
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Tick repeat;
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public:
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StatEvent(int _flags, Tick _when, Tick _repeat);
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virtual void process();
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virtual const char *description();
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};
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StatEvent::StatEvent(int _flags, Tick _when, Tick _repeat)
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: Event(&mainEventQueue, Stat_Event_Pri),
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flags(_flags), repeat(_repeat)
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{
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setFlags(AutoDelete);
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schedule(_when);
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}
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const char *
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StatEvent::description()
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{
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return "Statistics dump and/or reset";
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}
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void
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StatEvent::process()
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{
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if (flags & Stats::Dump)
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DumpNow();
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if (flags & Stats::Reset)
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reset();
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if (repeat)
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schedule(curTick + repeat);
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}
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list<Output *> OutputList;
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void
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DumpNow()
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{
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list<Output *>::iterator i = OutputList.begin();
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list<Output *>::iterator end = OutputList.end();
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for (; i != end; ++i) {
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Output *output = *i;
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if (!output->valid())
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continue;
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output->output();
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}
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}
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void
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SetupEvent(int flags, Tick when, Tick repeat)
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{
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new StatEvent(flags, when, repeat);
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}
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/* namespace Stats */ }
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extern "C" void
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debugDumpStats()
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{
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Stats::DumpNow();
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}
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