5eab6c4b41
CPU cycle ticks. This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency. For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.
arch/alpha/ev5.cc:
The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
frequency isn't the cpu parameter anymore, cycleTime is.
create several public functions for getting the cpu frequency
and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
Now that ticks aren't cpu cycles, fixup code to advance
by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
Provide a function to get the number of ticks for a given
number of cycles.
dev/alpha_console.cc:
Update for changes in the way that frequencies and latencies are
accessed. Move some stuff to init()
dev/alpha_console.hh:
Need a pointer to the system and the cpu to get the frequency
so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
outline the constructor and destructor
dev/platform.hh:
outline the constructor and destructor.
don't keep track of the interrupt frequency. Only provide the
accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
outline the constructor and destructor
Don't set the interrupt frequency here. Get it from the actual device
that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
Make the interrupt interval a configuration parameter. (And convert
the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
update for changes in the way bandwidths are passed from
python to C++ to accomidate the new way that ticks works.
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
kern/tru64/tru64_system.cc:
For now, we must get the boot cpu's frequency as a parameter
since allowing the system to have a pointer to the boot cpu would
cause a cycle.
python/m5/config.py:
Fix support for cycle_time relative latencies and frequencies.
Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
All CPUs now have a cycle_time. The default is the global frequency,
but it is now possible to set the global frequency to some large value
(like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
this frequency isn't needed. We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
The clock generator should hold the frequency
sim/eventq.hh:
Need to remove this assertion because the writeback event
queue is different from the CPU's event queue which can cause
this assertion to fail.
sim/process.cc:
Fix comment.
sim/system.hh:
Struct member to hold the boot CPU's frequency.
sim/universe.cc:
remove unneeded variable.
--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
120 lines
4.3 KiB
C++
120 lines
4.3 KiB
C++
/*
|
|
* Copyright (c) 2001-2004 The Regents of The University of Michigan
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
/* @file
|
|
* System Console Interface
|
|
*/
|
|
|
|
#ifndef __ALPHA_CONSOLE_HH__
|
|
#define __ALPHA_CONSOLE_HH__
|
|
|
|
#include "base/range.hh"
|
|
#include "dev/alpha_access.h"
|
|
#include "dev/io_device.hh"
|
|
#include "sim/host.hh"
|
|
#include "sim/sim_object.hh"
|
|
|
|
class BaseCPU;
|
|
class SimConsole;
|
|
class System;
|
|
class SimpleDisk;
|
|
|
|
/*
|
|
* Memory mapped interface to the system console. This device
|
|
* represents a shared data region between the OS Kernel and the
|
|
* System Console.
|
|
*
|
|
* The system console is a small standalone program that is initially
|
|
* run when the system boots. It contains the necessary code to
|
|
* access the boot disk, to read/write from the console, and to pass
|
|
* boot parameters to the kernel.
|
|
*
|
|
* This version of the system console is very different from the one
|
|
* that would be found in a real system. Many of the functions use
|
|
* some sort of backdoor to get their job done. For example, reading
|
|
* from the boot device on a real system would require a minimal
|
|
* device driver to access the disk controller, but since we have a
|
|
* simulator here, we are able to bypass the disk controller and
|
|
* access the disk image directly. There are also some things like
|
|
* reading the kernel off the disk image into memory that are normally
|
|
* taken care of by the console that are now taken care of by the
|
|
* simulator.
|
|
*
|
|
* These shortcuts are acceptable since the system console is
|
|
* primarily used doing boot before the kernel has loaded its device
|
|
* drivers.
|
|
*/
|
|
class AlphaConsole : public PioDevice
|
|
{
|
|
protected:
|
|
union {
|
|
AlphaAccess *alphaAccess;
|
|
uint8_t *consoleData;
|
|
};
|
|
|
|
/** the disk must be accessed from the console */
|
|
SimpleDisk *disk;
|
|
|
|
/** the system console (the terminal) is accessable from the console */
|
|
SimConsole *console;
|
|
|
|
/** a pointer to the system we are running in */
|
|
System *system;
|
|
|
|
/** a pointer to the CPU boot cpu */
|
|
BaseCPU *cpu;
|
|
|
|
Addr addr;
|
|
static const Addr size = 0x80; // equal to sizeof(alpha_access);
|
|
|
|
public:
|
|
/** Standard Constructor */
|
|
AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
|
|
System *s, BaseCPU *c, Platform *platform,
|
|
int num_cpus, MemoryController *mmu, Addr addr,
|
|
HierParams *hier, Bus *bus);
|
|
|
|
virtual void init();
|
|
|
|
/**
|
|
* memory mapped reads and writes
|
|
*/
|
|
virtual Fault read(MemReqPtr &req, uint8_t *data);
|
|
virtual Fault write(MemReqPtr &req, const uint8_t *data);
|
|
|
|
/**
|
|
* standard serialization routines for checkpointing
|
|
*/
|
|
virtual void serialize(std::ostream &os);
|
|
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
|
|
|
public:
|
|
Tick cacheAccess(MemReqPtr &req);
|
|
};
|
|
|
|
#endif // __ALPHA_CONSOLE_HH__
|