1516 lines
177 KiB
Text
1516 lines
177 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.802895 # Number of seconds simulated
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sim_ticks 2802894699500 # Number of ticks simulated
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final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 515393 # Simulator instruction rate (inst/s)
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host_op_rate 627998 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 9838648327 # Simulator tick rate (ticks/s)
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host_mem_usage 594196 # Number of bytes of host memory used
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host_seconds 284.89 # Real time elapsed on the host
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sim_insts 146828240 # Number of instructions simulated
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sim_ops 178908039 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 1108644 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 9410404 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1082576 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 11757100 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 1108644 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1262520 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 8452288 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
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system.physmem.bytes_written::total 8469852 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 25776 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 147557 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 16935 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 192852 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 132067 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 136458 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 395535 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 3357388 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 386235 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 4194628 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 395535 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 450434 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3015557 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 3021823 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3015557 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 395535 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 3363640 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 386249 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 7216451 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 631 # Number of DMA write transactions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu0.dtb.walker.walks 7967 # Table walker walks requested
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system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors
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system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
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system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
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system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
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system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated
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system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated
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system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.inst_hits 0 # ITB inst hits
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system.cpu0.dtb.inst_misses 0 # ITB inst misses
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system.cpu0.dtb.read_hits 20339720 # DTB read hits
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system.cpu0.dtb.read_misses 6874 # DTB read misses
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system.cpu0.dtb.write_hits 16391078 # DTB write hits
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system.cpu0.dtb.write_misses 1093 # DTB write misses
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system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
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system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
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system.cpu0.dtb.read_accesses 20346594 # DTB read accesses
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system.cpu0.dtb.write_accesses 16392171 # DTB write accesses
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu0.dtb.hits 36730798 # DTB hits
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system.cpu0.dtb.misses 7967 # DTB misses
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system.cpu0.dtb.accesses 36738765 # DTB accesses
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system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.walker.walks 3358 # Table walker walks requested
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|
system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors
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|
system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
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|
system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated
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system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated
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|
system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst
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|
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst
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|
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst
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|
system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst
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|
system.cpu0.itb.inst_hits 97439331 # ITB inst hits
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|
system.cpu0.itb.inst_misses 3358 # ITB inst misses
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|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses
|
|
system.cpu0.itb.hits 97439331 # DTB hits
|
|
system.cpu0.itb.misses 3358 # DTB misses
|
|
system.cpu0.itb.accesses 97442689 # DTB accesses
|
|
system.cpu0.numCycles 5605791368 # number of cpu cycles simulated
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|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed
|
|
system.cpu0.committedInsts 95426926 # Number of instructions committed
|
|
system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed
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|
system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
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|
system.cpu0.num_func_calls 8000180 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 100762696 # number of integer instructions
|
|
system.cpu0.num_fp_insts 9755 # number of float instructions
|
|
system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 37873810 # number of memory refs
|
|
system.cpu0.num_load_insts 20597310 # Number of load instructions
|
|
system.cpu0.num_store_insts 17276500 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles
|
|
system.cpu0.Branches 21941499 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 116882065 # Class of executed instruction
|
|
system.cpu0.dcache.tags.replacements 693486 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 15690389 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 15690389 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363050 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 363050 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 34798930 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 34798930 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 35145023 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 35145023 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 295796 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 295796 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18435 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 18435 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 769220 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048324 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048324 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 693486 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 693486 # number of writebacks
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 1109735 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 96331417 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1110256 # number of overall misses
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.writebacks::writebacks 1109735 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 1109735 # number of writebacks
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
|
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
|
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
|
system.cpu0.l2cache.tags.replacements 249527 # number of replacements
|
|
system.cpu0.l2cache.tags.tagsinuse 16129.991654 # Cycle average of tags in use
|
|
system.cpu0.l2cache.tags.total_refs 2731505 # Total number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.sampled_refs 265646 # Sample count of references to valid blocks.
|
|
system.cpu0.l2cache.tags.avg_refs 10.282500 # Average number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.l2cache.tags.occ_blocks::writebacks 16127.358870 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.556147 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076637 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_percent::writebacks 0.984336 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000156 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::total 0.984497 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16112 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5452 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7536 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2638 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983398 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.tag_accesses 59699237 # Number of tag accesses
|
|
system.cpu0.l2cache.tags.data_accesses 59699237 # Number of data accesses
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10182 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4496 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::total 14678 # number of ReadReq hits
|
|
system.cpu0.l2cache.WritebackDirty_hits::writebacks 510201 # number of WritebackDirty hits
|
|
system.cpu0.l2cache.WritebackDirty_hits::total 510201 # number of WritebackDirty hits
|
|
system.cpu0.l2cache.WritebackClean_hits::writebacks 1265145 # number of WritebackClean hits
|
|
system.cpu0.l2cache.WritebackClean_hits::total 1265145 # number of WritebackClean hits
|
|
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94344 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::total 94344 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068613 # number of ReadCleanReq hits
|
|
system.cpu0.l2cache.ReadCleanReq_hits::total 1068613 # number of ReadCleanReq hits
|
|
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352244 # number of ReadSharedReq hits
|
|
system.cpu0.l2cache.ReadSharedReq_hits::total 352244 # number of ReadSharedReq hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10182 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4496 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.inst 1068613 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.data 446588 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::total 1529879 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10182 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4496 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.inst 1068613 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.data 446588 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::total 1529879 # number of overall hits
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 130 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::total 344 # number of ReadReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26273 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::total 26273 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18435 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::total 18435 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175179 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::total 175179 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41643 # number of ReadCleanReq misses
|
|
system.cpu0.l2cache.ReadCleanReq_misses::total 41643 # number of ReadCleanReq misses
|
|
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127922 # number of ReadSharedReq misses
|
|
system.cpu0.l2cache.ReadSharedReq_misses::total 127922 # number of ReadSharedReq misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 130 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.inst 41643 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.data 303101 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::total 345088 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 130 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.inst 41643 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.data 303101 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::total 345088 # number of overall misses
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10396 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4626 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::total 15022 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510201 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackDirty_accesses::total 510201 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265145 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackClean_accesses::total 1265145 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18435 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::total 18435 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480166 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadSharedReq_accesses::total 480166 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10396 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4626 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::total 1874967 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10396 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4626 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::total 1874967 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028102 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::total 0.022900 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649959 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649959 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037508 # miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037508 # miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266412 # miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266412 # miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028102 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037508 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404302 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::total 0.184050 # miss rate for demand accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028102 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037508 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404302 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::total 0.184050 # miss rate for overall accesses
|
|
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.l2cache.writebacks::writebacks 192911 # number of writebacks
|
|
system.cpu0.l2cache.writebacks::total 192911 # number of writebacks
|
|
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.toL2Bus.snoop_filter.tot_requests 3720245 # Total number of requests made to the snoop filter.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860324 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.tot_snoops 218142 # Total number of snoops made to the snoop filter.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215248 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2894 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WritebackDirty 510201 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WritebackClean 1265145 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeReq 26273 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18435 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeResp 44708 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395284 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count::total 5764166 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140768632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92116612 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size::total 232968516 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.snoops 623122 # Total snoops (count)
|
|
system.cpu0.toL2Bus.snoop_fanout::samples 4318148 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::mean 0.066969 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::stdev 0.252635 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::0 4031861 93.37% 93.37% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::1 283393 6.56% 99.93% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::2 2894 0.07% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::total 4318148 # Request fanout histogram
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.walker.walks 3358 # Table walker walks requested
|
|
system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors
|
|
system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 12173916 # DTB read hits
|
|
system.cpu1.dtb.read_misses 2852 # DTB read misses
|
|
system.cpu1.dtb.write_hits 7587209 # DTB write hits
|
|
system.cpu1.dtb.write_misses 506 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 12176768 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 7587715 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 19761125 # DTB hits
|
|
system.cpu1.dtb.misses 3358 # DTB misses
|
|
system.cpu1.dtb.accesses 19764483 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.walker.walks 1734 # Table walker walks requested
|
|
system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors
|
|
system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.inst_hits 53671575 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 1734 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses
|
|
system.cpu1.itb.hits 53671575 # DTB hits
|
|
system.cpu1.itb.misses 1734 # DTB misses
|
|
system.cpu1.itb.accesses 53673309 # DTB accesses
|
|
system.cpu1.numCycles 5605320274 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
|
|
system.cpu1.committedInsts 51401314 # Number of instructions committed
|
|
system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 9170855 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 56984241 # number of integer instructions
|
|
system.cpu1.num_fp_insts 1792 # number of float instructions
|
|
system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 20026381 # number of memory refs
|
|
system.cpu1.num_load_insts 12289537 # Number of load instructions
|
|
system.cpu1.num_store_insts 7736844 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles
|
|
system.cpu1.Branches 15217493 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 65459464 # Class of executed instruction
|
|
system.cpu1.dcache.tags.replacements 191938 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 7397500 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 7397500 # number of WriteReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 19256194 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 19256194 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 19306293 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 19306293 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 92462 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 92462 # number of WriteReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 259811 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 259811 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237347 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237347 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 191938 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 191938 # number of writebacks
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 523373 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 53148780 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 523885 # number of overall misses
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.writebacks::writebacks 523373 # number of writebacks
|
|
system.cpu1.icache.writebacks::total 523373 # number of writebacks
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
|
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
|
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
|
system.cpu1.l2cache.tags.replacements 47555 # number of replacements
|
|
system.cpu1.l2cache.tags.tagsinuse 15235.297156 # Cycle average of tags in use
|
|
system.cpu1.l2cache.tags.total_refs 1184961 # Total number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.sampled_refs 62593 # Sample count of references to valid blocks.
|
|
system.cpu1.l2cache.tags.avg_refs 18.931206 # Average number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.l2cache.tags.occ_blocks::writebacks 15230.950549 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.335617 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010990 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_percent::writebacks 0.929623 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::total 0.929889 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15019 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 530 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9526 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4963 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.916687 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.tag_accesses 24500378 # Number of tag accesses
|
|
system.cpu1.l2cache.tags.data_accesses 24500378 # Number of data accesses
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1913 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::total 5534 # number of ReadReq hits
|
|
system.cpu1.l2cache.WritebackDirty_hits::writebacks 121109 # number of WritebackDirty hits
|
|
system.cpu1.l2cache.WritebackDirty_hits::total 121109 # number of WritebackDirty hits
|
|
system.cpu1.l2cache.WritebackClean_hits::writebacks 583044 # number of WritebackClean hits
|
|
system.cpu1.l2cache.WritebackClean_hits::total 583044 # number of WritebackClean hits
|
|
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19763 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::total 19763 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510346 # number of ReadCleanReq hits
|
|
system.cpu1.l2cache.ReadCleanReq_hits::total 510346 # number of ReadCleanReq hits
|
|
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99093 # number of ReadSharedReq hits
|
|
system.cpu1.l2cache.ReadSharedReq_hits::total 99093 # number of ReadSharedReq hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1913 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.inst 510346 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.data 118856 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::total 634736 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1913 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.inst 510346 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.data 118856 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::total 634736 # number of overall hits
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::total 607 # number of ReadReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43853 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::total 43853 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13539 # number of ReadCleanReq misses
|
|
system.cpu1.l2cache.ReadCleanReq_misses::total 13539 # number of ReadCleanReq misses
|
|
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73574 # number of ReadSharedReq misses
|
|
system.cpu1.l2cache.ReadSharedReq_misses::total 73574 # number of ReadSharedReq misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.inst 13539 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.data 117427 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.inst 13539 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.data 117427 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3957 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2184 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121109 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackDirty_accesses::total 121109 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackClean_accesses::writebacks 583044 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackClean_accesses::total 583044 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172667 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadSharedReq_accesses::total 172667 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3957 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2184 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::total 766309 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3957 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2184 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::total 766309 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124084 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::total 0.098844 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689339 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689339 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025843 # miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025843 # miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.426103 # miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.426103 # miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124084 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025843 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496976 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::total 0.171697 # miss rate for demand accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124084 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025843 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496976 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::total 0.171697 # miss rate for overall accesses
|
|
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.l2cache.writebacks::writebacks 32818 # number of writebacks
|
|
system.cpu1.l2cache.writebacks::total 32818 # number of writebacks
|
|
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.toL2Bus.snoop_filter.tot_requests 1533421 # Total number of requests made to the snoop filter.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773256 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.tot_snoops 165978 # Total number of snoops made to the snoop filter.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164041 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WritebackDirty 121109 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WritebackClean 583044 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeResp 51389 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776509 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count::total 2357775 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66454020 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27282414 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size::total 93773822 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.snoops 347349 # Total snoops (count)
|
|
system.cpu1.toL2Bus.snoop_fanout::samples 1819817 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::mean 0.108136 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::stdev 0.313960 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::0 1624967 89.29% 89.29% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::1 192913 10.60% 99.89% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::2 1937 0.11% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::total 1819817 # Request fanout histogram
|
|
system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 59419 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iocache.tags.replacements 36442 # number of replacements
|
|
system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328284 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 252 # number of overall misses
|
|
system.iocache.overall_misses::total 252 # number of overall misses
|
|
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 107037 # number of replacements
|
|
system.l2c.tags.tagsinuse 62176.956554 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 241620 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 167464 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 1.442818 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 47954.224141 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010653 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030815 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 7778.474758 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 4056.241083 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 1664.556464 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 718.418639 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.731723 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.118690 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.061893 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.025399 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.010962 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.948745 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 60421 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 1839 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 45269 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.921951 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 5183068 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 5183068 # Number of data accesses
|
|
system.l2c.WritebackDirty_hits::writebacks 225729 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 225729 # number of WritebackDirty hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 511 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 575 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 13894 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 3132 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 17026 # number of ReadExReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 74 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.inst 24882 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 76059 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.inst 11145 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 11759 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 124050 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 24882 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 89953 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 11145 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 14891 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 141076 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 24882 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 89953 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 11145 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 14891 # number of overall hits
|
|
system.l2c.overall_hits::total 141076 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 10043 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 13338 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1932 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 136525 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 15837 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 152362 # number of ReadExReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.inst 16761 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 11173 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 1126 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 31464 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 16761 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 147698 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 16963 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 183826 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 16761 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 147698 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 16963 # number of overall misses
|
|
system.l2c.overall_misses::total 183826 # number of overall misses
|
|
system.l2c.WritebackDirty_accesses::writebacks 225729 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 225729 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 10554 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 3359 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 13913 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 1185 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 150419 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 18969 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 169388 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 82 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 70 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.inst 41643 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 87232 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 27 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.inst 13539 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 12885 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 155514 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 82 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 41643 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 237651 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 13539 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 31854 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 324902 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 82 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 41643 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 237651 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 13539 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 31854 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 324902 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951582 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980947 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.958672 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920635 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994093 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.964072 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.907631 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.834889 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.899485 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028571 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402493 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128084 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176823 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087388 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.202323 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.028571 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.402493 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.621491 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.176823 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.532523 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.565789 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.028571 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.402493 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.621491 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.176823 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.532523 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.565789 # miss rate for overall accesses
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 95877 # number of writebacks
|
|
system.l2c.writebacks::total 95877 # number of writebacks
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 43996 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 75712 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 30846 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 30846 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 132067 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 8465 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 60519 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 15741 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 196031 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 151891 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660645 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 782029 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 891184 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17927560 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 18117342 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 20449630 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 581009 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 581009 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 581009 # Request fanout histogram
|
|
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
|
system.toL2Bus.snoop_filter.tot_requests 863003 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 444472 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 128485 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 9552 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 9071 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 481 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 301629 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 225729 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 38612 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 60623 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 40978 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 101601 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 213528 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 213528 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 257629 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1143706 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 415843 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 1559549 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34428348 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10418866 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 44847214 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 180208 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 1117804 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.282168 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.451010 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 802876 71.83% 71.83% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 314447 28.13% 99.96% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 481 0.04% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 1117804 # Request fanout histogram
|
|
|
|
---------- End Simulation Statistics ----------
|