885 lines
102 KiB
Text
885 lines
102 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.056961 # Number of seconds simulated
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sim_ticks 56960656500 # Number of ticks simulated
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final_tick 56960656500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 199606 # Simulator instruction rate (inst/s)
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host_op_rate 255266 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 160327771 # Simulator tick rate (ticks/s)
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host_mem_usage 325784 # Number of bytes of host memory used
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host_seconds 355.28 # Real time elapsed on the host
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sim_insts 70915128 # Number of instructions simulated
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sim_ops 90690084 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 285184 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7924608 # Number of bytes read from this memory
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system.physmem.bytes_read::total 8209792 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 285184 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 285184 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 5517504 # Number of bytes written to this memory
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system.physmem.bytes_written::total 5517504 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 4456 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 123822 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 128278 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 86211 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 86211 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 5006684 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 139124239 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 144130923 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 5006684 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 5006684 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 96865176 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 96865176 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 96865176 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 5006684 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 139124239 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 240996099 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 128278 # Number of read requests accepted
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system.physmem.writeReqs 86211 # Number of write requests accepted
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system.physmem.readBursts 128278 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 86211 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 8209408 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
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system.physmem.bytesWritten 5515712 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 8209792 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 6908 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 8061 # Per bank write bursts
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system.physmem.perBankRdBursts::1 8314 # Per bank write bursts
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system.physmem.perBankRdBursts::2 8233 # Per bank write bursts
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system.physmem.perBankRdBursts::3 8140 # Per bank write bursts
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system.physmem.perBankRdBursts::4 8284 # Per bank write bursts
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system.physmem.perBankRdBursts::5 8402 # Per bank write bursts
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system.physmem.perBankRdBursts::6 8056 # Per bank write bursts
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system.physmem.perBankRdBursts::7 7915 # Per bank write bursts
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system.physmem.perBankRdBursts::8 8035 # Per bank write bursts
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system.physmem.perBankRdBursts::9 7586 # Per bank write bursts
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system.physmem.perBankRdBursts::10 7763 # Per bank write bursts
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system.physmem.perBankRdBursts::11 7815 # Per bank write bursts
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system.physmem.perBankRdBursts::12 7871 # Per bank write bursts
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system.physmem.perBankRdBursts::13 7867 # Per bank write bursts
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system.physmem.perBankRdBursts::14 7968 # Per bank write bursts
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system.physmem.perBankRdBursts::15 7962 # Per bank write bursts
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system.physmem.perBankWrBursts::0 5394 # Per bank write bursts
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system.physmem.perBankWrBursts::1 5541 # Per bank write bursts
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system.physmem.perBankWrBursts::2 5465 # Per bank write bursts
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system.physmem.perBankWrBursts::3 5335 # Per bank write bursts
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system.physmem.perBankWrBursts::4 5367 # Per bank write bursts
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system.physmem.perBankWrBursts::5 5560 # Per bank write bursts
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system.physmem.perBankWrBursts::6 5259 # Per bank write bursts
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system.physmem.perBankWrBursts::7 5181 # Per bank write bursts
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system.physmem.perBankWrBursts::8 5155 # Per bank write bursts
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system.physmem.perBankWrBursts::9 5101 # Per bank write bursts
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system.physmem.perBankWrBursts::10 5292 # Per bank write bursts
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system.physmem.perBankWrBursts::11 5270 # Per bank write bursts
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system.physmem.perBankWrBursts::12 5531 # Per bank write bursts
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system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
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system.physmem.perBankWrBursts::14 5703 # Per bank write bursts
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system.physmem.perBankWrBursts::15 5432 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 56960630500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 128278 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 86211 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 116041 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 12210 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 661 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 668 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4041 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5199 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5309 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5322 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5319 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 5319 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 5327 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5345 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5368 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 5411 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 5463 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5462 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5300 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 38843 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 353.305769 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 214.370646 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 335.820424 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 12327 31.74% 31.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 8308 21.39% 53.12% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 4009 10.32% 63.45% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2908 7.49% 70.93% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2579 6.64% 77.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1645 4.23% 81.81% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1295 3.33% 85.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1183 3.05% 88.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 4589 11.81% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 38843 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 24.231438 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 352.038332 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.282449 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.265601 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 0.771117 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 4623 87.34% 87.34% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 6 0.11% 87.46% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 534 10.09% 97.54% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 111 2.10% 99.64% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20 13 0.25% 99.89% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads
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system.physmem.totQLat 1678352000 # Total ticks spent queuing
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system.physmem.totMemAccLat 4083452000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 641360000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 13084.32 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 31834.32 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 144.12 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 96.83 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 144.13 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 96.87 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 1.88 # Data bus utilization in percentage
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system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing
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system.physmem.readRowHits 111810 # Number of row buffer hits during reads
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system.physmem.writeRowHits 63793 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes
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system.physmem.avgGap 265564.34 # Average gap between requests
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system.physmem.pageHitRate 81.87 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 153158040 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 83568375 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 509862600 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 11565367830 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 24028947750 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 40340244195 # Total energy per rank (pJ)
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system.physmem_0.averagePower 708.261877 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 39847901500 # Time in different power states
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system.physmem_0.memoryStateTime::REF 1901900000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 15206891000 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 140419440 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 76617750 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 490214400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 10938128715 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 24579157500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 40223793165 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 706.217322 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 40763292250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1901900000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 14291603250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 14800638 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 9905777 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 381686 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 9438449 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 6732187 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 71.327259 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 1714133 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
|
system.cpu.numCycles 113921313 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 70915128 # Number of instructions committed
|
|
system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 1144928 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.606446 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.622492 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 95595424 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 18325889 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 156436 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4067.127430 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 42624259 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 160532 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 265.518769 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127430 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1105 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2947 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 86016734 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 86016734 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 22866824 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 22866824 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 19642179 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 19642179 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 83418 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 83418 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 42509003 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 42509003 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 42592421 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 42592421 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 51533 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 51533 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 207722 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 207722 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 44587 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 44587 # number of SoftPFReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 259255 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 259255 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 303842 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 303842 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489955500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 1489955500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16807631000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 16807631000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 18297586500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 18297586500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 18297586500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 18297586500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 128005 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348322 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.348322 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28912.648206 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 28912.648206 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80914.063027 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 80914.063027 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70577.564560 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 70577.564560 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60220.728207 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 60220.728207 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 128377 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 128377 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22014 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 22014 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100694 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 100694 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 122708 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 122708 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 122708 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 122708 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29519 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 29519 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 136547 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 136547 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 160532 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 160532 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 577658500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 577658500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488450500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488450500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1712416500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1712416500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9066109000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 9066109000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10778525500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10778525500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187375 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187375 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19569.040279 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19569.040279 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79310.558919 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79310.558919 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71395.309568 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71395.309568 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66395.519491 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66395.519491 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67142.535445 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67142.535445 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 42868 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1852.481887 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 24941232 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 44910 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 555.360321 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1852.481887 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.904532 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.904532 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 50017196 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 50017196 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 24941232 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 24941232 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 24941232 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 24941232 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 24941232 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 24941232 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 44911 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 44911 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 44911 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 44911 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 44911 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 44911 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 896725000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 896725000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 896725000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 896725000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 896725000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 896725000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 24986143 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 24986143 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 24986143 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 24986143 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 24986143 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 24986143 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19966.711941 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 19966.711941 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 19966.711941 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 19966.711941 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 42868 # number of writebacks
|
|
system.cpu.icache.writebacks::total 42868 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44911 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 44911 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 44911 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 44911 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 44911 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 44911 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 851815000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 851815000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 851815000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 851815000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 851815000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 851815000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18966.734208 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18966.734208 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 96386 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 29871.418055 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 162162 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 127539 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 1.271470 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 26782.423909 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1431.670582 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 1657.323564 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.817335 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043691 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.050578 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.911603 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31153 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1851 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12724 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15788 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 593 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 3410031 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 3410031 # Number of data accesses
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 128377 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 128377 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 39288 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 39288 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 40441 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 40441 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31897 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 31897 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 40441 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 36648 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 77089 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 40441 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 36648 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 77089 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 102277 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 102277 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4470 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 4470 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21607 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 21607 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 4470 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 123884 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 128354 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 4470 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 123884 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 128354 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8277973500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 8277973500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 355961000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 355961000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1870485000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1870485000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 355961000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10148458500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 10504419500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 355961000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10148458500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 10504419500 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 128377 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 128377 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 39288 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 39288 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44911 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 44911 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53504 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 53504 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 44911 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 160532 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 205443 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 44911 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 160532 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 205443 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955610 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955610 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.099530 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.099530 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403839 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403839 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099530 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.771709 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.624767 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099530 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.771709 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.624767 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80936.803974 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80936.803974 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79633.333333 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79633.333333 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86568.473180 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86568.473180 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 81839.440142 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 81839.440142 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 86211 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 86211 # number of writebacks
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102277 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 102277 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4457 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4457 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21545 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21545 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 4457 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 123822 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 128279 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4457 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 123822 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 128279 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7255203500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7255203500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310493500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310493500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1649955000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1649955000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310493500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8905158500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9215652000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310493500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8905158500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9215652000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955610 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955610 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099241 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402680 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402680 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.624402 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.624402 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70936.803974 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70936.803974 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69664.236033 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69664.236033 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76581.805523 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76581.805523 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 404747 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 199340 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 3362 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 98414 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 214588 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 39288 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 34000 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 44911 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 53504 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129109 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473266 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 602375 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5388672 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490176 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 23878848 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 96386 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 301829 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.037243 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.189864 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 290617 96.29% 96.29% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 11183 3.71% 99.99% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 301829 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 373618500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 67384461 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 240832431 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 26001 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 86211 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 6908 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 102277 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 102277 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 26001 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349675 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 349675 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 13727296 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 221397 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 221397 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 221397 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 590585500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 676907000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|