Anthony Gutierrez 8a53da22c2 cpu: allow the fetch buffer to be smaller than a cache line ... the current implementation of the fetch buffer in the o3 cpu is only allowed to be the size of a cache line. some architectures, e.g., ARM, have fetch buffers smaller than a cache line, see slide 22 at: http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf this patch allows the fetch buffer to be set to values smaller than a cache line.		2013-11-15 13:21:15 -05:00
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Benchmarks.py	configs: add run scripts for ics/gb versions of android and bbench	2012-06-11 11:07:42 -04:00
CacheConfig.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
Caches.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
cpu2000.py	cpu2000: Add missing art benchmark to all	2012-01-09 18:08:20 -06:00
CpuConfig.py	config: Add a 'kvm' CPU alias	2013-09-30 09:45:43 +02:00
FSConfig.py	arm, config: Fix a small issue with the dtb file being specified	2013-10-17 10:20:45 -05:00
MemConfig.py	config: Command line support for multi-channel memory	2013-08-19 03:52:34 -04:00
O3_ARM_v7a.py	cpu: allow the fetch buffer to be smaller than a cache line	2013-11-15 13:21:15 -05:00
Options.py	util: Streamline .apc project convertsion script	2013-10-17 10:20:45 -05:00
Simulation.py	config: Initialize and check cpt_starttick	2013-09-11 15:34:21 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00