de72e36619
this patch adds an ordered response buffer to the GM pipeline to ensure in-order data delivery. the buffer is implemented as a stl ordered map, which sorts the request in program order by using their sequence ID. when requests return to the GM pipeline they are marked as done. only the oldest request may be serviced from the ordered buffer, and only if is marked as done. the FIFO response buffers are kept and used in OoO delivery mode
580 lines
24 KiB
Python
580 lines
24 KiB
Python
#
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# Copyright (c) 2015 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# For use for simulation and test purposes only
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its contributors
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# may be used to endorse or promote products derived from this software
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# without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Sooraj Puthoor
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#
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import optparse, os, re
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import math
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import glob
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import inspect
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import m5
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from m5.objects import *
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from m5.util import addToPath
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addToPath('../')
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from ruby import Ruby
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from common import Options
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from common import Simulation
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from common import GPUTLBOptions, GPUTLBConfig
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########################## Script Options ########################
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def setOption(parser, opt_str, value = 1):
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# check to make sure the option actually exists
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if not parser.has_option(opt_str):
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raise Exception("cannot find %s in list of possible options" % opt_str)
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opt = parser.get_option(opt_str)
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# set the value
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exec("parser.values.%s = %s" % (opt.dest, value))
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def getOption(parser, opt_str):
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# check to make sure the option actually exists
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if not parser.has_option(opt_str):
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raise Exception("cannot find %s in list of possible options" % opt_str)
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opt = parser.get_option(opt_str)
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# get the value
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exec("return_value = parser.values.%s" % opt.dest)
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return return_value
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# Adding script options
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addSEOptions(parser)
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parser.add_option("--cpu-only-mode", action="store_true", default=False,
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help="APU mode. Used to take care of problems in "\
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"Ruby.py while running APU protocols")
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parser.add_option("-k", "--kernel-files",
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help="file(s) containing GPU kernel code (colon separated)")
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parser.add_option("-u", "--num-compute-units", type="int", default=1,
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help="number of GPU compute units"),
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parser.add_option("--num-cp", type="int", default=0,
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help="Number of GPU Command Processors (CP)")
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parser.add_option("--benchmark-root", help="Root of benchmark directory tree")
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# not super important now, but to avoid putting the number 4 everywhere, make
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# it an option/knob
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parser.add_option("--cu-per-sqc", type="int", default=4, help="number of CUs" \
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"sharing an SQC (icache, and thus icache TLB)")
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parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \
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"per CU")
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parser.add_option("--wf-size", type="int", default=64,
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help="Wavefront size(in workitems)")
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parser.add_option("--sp-bypass-path-length", type="int", default=4, \
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help="Number of stages of bypass path in vector ALU for Single Precision ops")
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parser.add_option("--dp-bypass-path-length", type="int", default=4, \
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help="Number of stages of bypass path in vector ALU for Double Precision ops")
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# issue period per SIMD unit: number of cycles before issuing another vector
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parser.add_option("--issue-period", type="int", default=4, \
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help="Number of cycles per vector instruction issue period")
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parser.add_option("--glbmem-wr-bus-width", type="int", default=32, \
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help="VGPR to Coalescer (Global Memory) data bus width in bytes")
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parser.add_option("--glbmem-rd-bus-width", type="int", default=32, \
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help="Coalescer to VGPR (Global Memory) data bus width in bytes")
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# Currently we only support 1 local memory pipe
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parser.add_option("--shr-mem-pipes-per-cu", type="int", default=1, \
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help="Number of Shared Memory pipelines per CU")
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# Currently we only support 1 global memory pipe
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parser.add_option("--glb-mem-pipes-per-cu", type="int", default=1, \
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help="Number of Global Memory pipelines per CU")
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parser.add_option("--wfs-per-simd", type="int", default=10, help="Number of " \
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"WF slots per SIMD")
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parser.add_option("--vreg-file-size", type="int", default=2048,
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help="number of physical vector registers per SIMD")
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parser.add_option("--bw-scalor", type="int", default=0,
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help="bandwidth scalor for scalability analysis")
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parser.add_option("--CPUClock", type="string", default="2GHz",
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help="CPU clock")
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parser.add_option("--GPUClock", type="string", default="1GHz",
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help="GPU clock")
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parser.add_option("--cpu-voltage", action="store", type="string",
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default='1.0V',
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help = """CPU voltage domain""")
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parser.add_option("--gpu-voltage", action="store", type="string",
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default='1.0V',
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help = """CPU voltage domain""")
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parser.add_option("--CUExecPolicy", type="string", default="OLDEST-FIRST",
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help="WF exec policy (OLDEST-FIRST, ROUND-ROBIN)")
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parser.add_option("--xact-cas-mode", action="store_true",
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help="enable load_compare mode (transactional CAS)")
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parser.add_option("--SegFaultDebug",action="store_true",
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help="checks for GPU seg fault before TLB access")
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parser.add_option("--FunctionalTLB",action="store_true",
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help="Assumes TLB has no latency")
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parser.add_option("--LocalMemBarrier",action="store_true",
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help="Barrier does not wait for writethroughs to complete")
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parser.add_option("--countPages", action="store_true",
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help="Count Page Accesses and output in per-CU output files")
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parser.add_option("--TLB-prefetch", type="int", help = "prefetch depth for"\
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"TLBs")
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parser.add_option("--pf-type", type="string", help="type of prefetch: "\
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"PF_CU, PF_WF, PF_PHASE, PF_STRIDE")
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parser.add_option("--pf-stride", type="int", help="set prefetch stride")
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parser.add_option("--numLdsBanks", type="int", default=32,
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help="number of physical banks per LDS module")
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parser.add_option("--ldsBankConflictPenalty", type="int", default=1,
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help="number of cycles per LDS bank conflict")
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parser.add_option('--fast-forward-pseudo-op', action='store_true',
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help = 'fast forward using kvm until the m5_switchcpu'
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' pseudo-op is encountered, then switch cpus. subsequent'
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' m5_switchcpu pseudo-ops will toggle back and forth')
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parser.add_option('--outOfOrderDataDelivery', action='store_true',
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default=False, help='enable OoO data delivery in the GM'
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' pipeline')
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Ruby.define_options(parser)
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#add TLB options to the parser
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GPUTLBOptions.tlb_options(parser)
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(options, args) = parser.parse_args()
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# The GPU cache coherence protocols only work with the backing store
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setOption(parser, "--access-backing-store")
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# if benchmark root is specified explicitly, that overrides the search path
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if options.benchmark_root:
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benchmark_path = [options.benchmark_root]
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else:
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# Set default benchmark search path to current dir
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benchmark_path = ['.']
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########################## Sanity Check ########################
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# Currently the gpu model requires ruby
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if buildEnv['PROTOCOL'] == 'None':
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fatal("GPU model requires ruby")
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# Currently the gpu model requires only timing or detailed CPU
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if not (options.cpu_type == "timing" or
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options.cpu_type == "detailed"):
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fatal("GPU model requires timing or detailed CPU")
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# This file can support multiple compute units
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assert(options.num_compute_units >= 1)
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# Currently, the sqc (I-Cache of GPU) is shared by
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# multiple compute units(CUs). The protocol works just fine
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# even if sqc is not shared. Overriding this option here
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# so that the user need not explicitly set this (assuming
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# sharing sqc is the common usage)
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n_cu = options.num_compute_units
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num_sqc = int(math.ceil(float(n_cu) / options.cu_per_sqc))
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options.num_sqc = num_sqc # pass this to Ruby
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########################## Creating the GPU system ########################
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# shader is the GPU
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shader = Shader(n_wf = options.wfs_per_simd,
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clk_domain = SrcClockDomain(
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clock = options.GPUClock,
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voltage_domain = VoltageDomain(
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voltage = options.gpu_voltage)))
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# GPU_RfO(Read For Ownership) implements SC/TSO memory model.
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# Other GPU protocols implement release consistency at GPU side.
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# So, all GPU protocols other than GPU_RfO should make their writes
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# visible to the global memory and should read from global memory
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# during kernal boundary. The pipeline initiates(or do not initiate)
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# the acquire/release operation depending on this impl_kern_boundary_sync
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# flag. This flag=true means pipeline initiates a acquire/release operation
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# at kernel boundary.
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if buildEnv['PROTOCOL'] == 'GPU_RfO':
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shader.impl_kern_boundary_sync = False
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else:
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shader.impl_kern_boundary_sync = True
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# Switching off per-lane TLB by default
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per_lane = False
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if options.TLB_config == "perLane":
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per_lane = True
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# List of compute units; one GPU can have multiple compute units
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compute_units = []
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for i in xrange(n_cu):
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compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane,
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num_SIMDs = options.simds_per_cu,
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wfSize = options.wf_size,
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spbypass_pipe_length = options.sp_bypass_path_length,
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dpbypass_pipe_length = options.dp_bypass_path_length,
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issue_period = options.issue_period,
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coalescer_to_vrf_bus_width = \
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options.glbmem_rd_bus_width,
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vrf_to_coalescer_bus_width = \
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options.glbmem_wr_bus_width,
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num_global_mem_pipes = \
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options.glb_mem_pipes_per_cu,
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num_shared_mem_pipes = \
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options.shr_mem_pipes_per_cu,
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n_wf = options.wfs_per_simd,
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execPolicy = options.CUExecPolicy,
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xactCasMode = options.xact_cas_mode,
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debugSegFault = options.SegFaultDebug,
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functionalTLB = options.FunctionalTLB,
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localMemBarrier = options.LocalMemBarrier,
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countPages = options.countPages,
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localDataStore = \
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LdsState(banks = options.numLdsBanks,
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bankConflictPenalty = \
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options.ldsBankConflictPenalty),
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out_of_order_data_delivery =
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options.outOfOrderDataDelivery))
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wavefronts = []
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vrfs = []
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for j in xrange(options.simds_per_cu):
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for k in xrange(shader.n_wf):
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wavefronts.append(Wavefront(simdId = j, wf_slot_id = k,
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wfSize = options.wf_size))
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vrfs.append(VectorRegisterFile(simd_id=j,
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num_regs_per_simd=options.vreg_file_size))
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compute_units[-1].wavefronts = wavefronts
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compute_units[-1].vector_register_file = vrfs
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if options.TLB_prefetch:
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compute_units[-1].prefetch_depth = options.TLB_prefetch
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compute_units[-1].prefetch_prev_type = options.pf_type
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# attach the LDS and the CU to the bus (actually a Bridge)
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compute_units[-1].ldsPort = compute_units[-1].ldsBus.slave
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compute_units[-1].ldsBus.master = compute_units[-1].localDataStore.cuPort
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# Attach compute units to GPU
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shader.CUs = compute_units
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########################## Creating the CPU system ########################
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options.num_cpus = options.num_cpus
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# The shader core will be whatever is after the CPU cores are accounted for
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shader_idx = options.num_cpus
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# The command processor will be whatever is after the shader is accounted for
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cp_idx = shader_idx + 1
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cp_list = []
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# List of CPUs
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cpu_list = []
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CpuClass, mem_mode = Simulation.getCPUClass(options.cpu_type)
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if CpuClass == AtomicSimpleCPU:
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fatal("AtomicSimpleCPU is not supported")
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if mem_mode != 'timing':
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fatal("Only the timing memory mode is supported")
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shader.timing = True
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if options.fast_forward and options.fast_forward_pseudo_op:
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fatal("Cannot fast-forward based both on the number of instructions and"
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" on pseudo-ops")
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fast_forward = options.fast_forward or options.fast_forward_pseudo_op
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if fast_forward:
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FutureCpuClass, future_mem_mode = CpuClass, mem_mode
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CpuClass = X86KvmCPU
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mem_mode = 'atomic_noncaching'
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# Leave shader.timing untouched, because its value only matters at the
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# start of the simulation and because we require switching cpus
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# *before* the first kernel launch.
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future_cpu_list = []
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# Initial CPUs to be used during fast-forwarding.
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for i in xrange(options.num_cpus):
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cpu = CpuClass(cpu_id = i,
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clk_domain = SrcClockDomain(
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clock = options.CPUClock,
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voltage_domain = VoltageDomain(
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voltage = options.cpu_voltage)))
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cpu_list.append(cpu)
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if options.fast_forward:
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cpu.max_insts_any_thread = int(options.fast_forward)
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if fast_forward:
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MainCpuClass = FutureCpuClass
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else:
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MainCpuClass = CpuClass
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# CPs to be used throughout the simulation.
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for i in xrange(options.num_cp):
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cp = MainCpuClass(cpu_id = options.num_cpus + i,
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clk_domain = SrcClockDomain(
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clock = options.CPUClock,
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voltage_domain = VoltageDomain(
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voltage = options.cpu_voltage)))
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cp_list.append(cp)
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# Main CPUs (to be used after fast-forwarding if fast-forwarding is specified).
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for i in xrange(options.num_cpus):
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cpu = MainCpuClass(cpu_id = i,
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clk_domain = SrcClockDomain(
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clock = options.CPUClock,
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voltage_domain = VoltageDomain(
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voltage = options.cpu_voltage)))
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if fast_forward:
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cpu.switched_out = True
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future_cpu_list.append(cpu)
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else:
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cpu_list.append(cpu)
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########################## Creating the GPU dispatcher ########################
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# Dispatcher dispatches work from host CPU to GPU
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host_cpu = cpu_list[0]
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dispatcher = GpuDispatcher()
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########################## Create and assign the workload ########################
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# Check for rel_path in elements of base_list using test, returning
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# the first full path that satisfies test
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def find_path(base_list, rel_path, test):
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for base in base_list:
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if not base:
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# base could be None if environment var not set
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continue
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full_path = os.path.join(base, rel_path)
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if test(full_path):
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return full_path
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fatal("%s not found in %s" % (rel_path, base_list))
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def find_file(base_list, rel_path):
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return find_path(base_list, rel_path, os.path.isfile)
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executable = find_path(benchmark_path, options.cmd, os.path.exists)
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# it's common for a benchmark to be in a directory with the same
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# name as the executable, so we handle that automatically
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if os.path.isdir(executable):
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benchmark_path = [executable]
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executable = find_file(benchmark_path, options.cmd)
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if options.kernel_files:
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kernel_files = [find_file(benchmark_path, f)
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for f in options.kernel_files.split(':')]
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else:
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# if kernel_files is not set, see if there's a unique .asm file
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# in the same directory as the executable
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kernel_path = os.path.dirname(executable)
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kernel_files = glob.glob(os.path.join(kernel_path, '*.asm'))
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if kernel_files:
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print "Using GPU kernel code file(s)", ",".join(kernel_files)
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else:
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fatal("Can't locate kernel code (.asm) in " + kernel_path)
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# OpenCL driver
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driver = ClDriver(filename="hsa", codefile=kernel_files)
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for cpu in cpu_list:
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cpu.workload = LiveProcess(executable = executable,
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cmd = [options.cmd] + options.options.split(),
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drivers = [driver])
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for cp in cp_list:
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cp.workload = host_cpu.workload
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if fast_forward:
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for i in xrange(len(future_cpu_list)):
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future_cpu_list[i].workload = cpu_list[i].workload
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########################## Create the overall system ########################
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# List of CPUs that must be switched when moving between KVM and simulation
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if fast_forward:
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switch_cpu_list = \
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[(cpu_list[i], future_cpu_list[i]) for i in xrange(options.num_cpus)]
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# Full list of processing cores in the system. Note that
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# dispatcher is also added to cpu_list although it is
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# not a processing element
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cpu_list = cpu_list + [shader] + cp_list + [dispatcher]
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# creating the overall system
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# notice the cpu list is explicitly added as a parameter to System
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system = System(cpu = cpu_list,
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mem_ranges = [AddrRange(options.mem_size)],
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cache_line_size = options.cacheline_size,
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mem_mode = mem_mode)
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if fast_forward:
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system.future_cpu = future_cpu_list
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system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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system.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = system.voltage_domain)
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if fast_forward:
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have_kvm_support = 'BaseKvmCPU' in globals()
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if have_kvm_support and buildEnv['TARGET_ISA'] == "x86":
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system.vm = KvmVM()
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for i in xrange(len(host_cpu.workload)):
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host_cpu.workload[i].useArchPT = True
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host_cpu.workload[i].kvmInSE = True
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else:
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fatal("KvmCPU can only be used in SE mode with x86")
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# configure the TLB hierarchy
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GPUTLBConfig.config_tlb_hierarchy(options, system, shader_idx)
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# create Ruby system
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system.piobus = IOXBar(width=32, response_latency=0,
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frontend_latency=0, forward_latency=0)
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Ruby.create_system(options, None, system)
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system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = system.voltage_domain)
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# attach the CPU ports to Ruby
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for i in range(options.num_cpus):
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ruby_port = system.ruby._cpu_ports[i]
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# Create interrupt controller
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system.cpu[i].createInterruptController()
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# Connect cache port's to ruby
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system.cpu[i].icache_port = ruby_port.slave
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system.cpu[i].dcache_port = ruby_port.slave
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ruby_port.mem_master_port = system.piobus.slave
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if buildEnv['TARGET_ISA'] == "x86":
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system.cpu[i].interrupts[0].pio = system.piobus.master
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system.cpu[i].interrupts[0].int_master = system.piobus.slave
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system.cpu[i].interrupts[0].int_slave = system.piobus.master
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if fast_forward:
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system.cpu[i].itb.walker.port = ruby_port.slave
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system.cpu[i].dtb.walker.port = ruby_port.slave
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# attach CU ports to Ruby
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# Because of the peculiarities of the CP core, you may have 1 CPU but 2
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# sequencers and thus 2 _cpu_ports created. Your GPUs shouldn't be
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# hooked up until after the CP. To make this script generic, figure out
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# the index as below, but note that this assumes there is one sequencer
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# per compute unit and one sequencer per SQC for the math to work out
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# correctly.
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gpu_port_idx = len(system.ruby._cpu_ports) \
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- options.num_compute_units - options.num_sqc
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gpu_port_idx = gpu_port_idx - options.num_cp * 2
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wavefront_size = options.wf_size
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for i in xrange(n_cu):
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# The pipeline issues wavefront_size number of uncoalesced requests
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# in one GPU issue cycle. Hence wavefront_size mem ports.
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for j in xrange(wavefront_size):
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system.cpu[shader_idx].CUs[i].memory_port[j] = \
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system.ruby._cpu_ports[gpu_port_idx].slave[j]
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gpu_port_idx += 1
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for i in xrange(n_cu):
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if i > 0 and not i % options.cu_per_sqc:
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print "incrementing idx on ", i
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gpu_port_idx += 1
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system.cpu[shader_idx].CUs[i].sqc_port = \
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system.ruby._cpu_ports[gpu_port_idx].slave
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gpu_port_idx = gpu_port_idx + 1
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# attach CP ports to Ruby
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for i in xrange(options.num_cp):
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system.cpu[cp_idx].createInterruptController()
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system.cpu[cp_idx].dcache_port = \
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system.ruby._cpu_ports[gpu_port_idx + i * 2].slave
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system.cpu[cp_idx].icache_port = \
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system.ruby._cpu_ports[gpu_port_idx + i * 2 + 1].slave
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system.cpu[cp_idx].interrupts[0].pio = system.piobus.master
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system.cpu[cp_idx].interrupts[0].int_master = system.piobus.slave
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system.cpu[cp_idx].interrupts[0].int_slave = system.piobus.master
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cp_idx = cp_idx + 1
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# connect dispatcher to the system.piobus
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dispatcher.pio = system.piobus.master
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dispatcher.dma = system.piobus.slave
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################# Connect the CPU and GPU via GPU Dispatcher ###################
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# CPU rings the GPU doorbell to notify a pending task
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# using this interface.
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# And GPU uses this interface to notify the CPU of task completion
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# The communcation happens through emulated driver.
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# Note this implicit setting of the cpu_pointer, shader_pointer and tlb array
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# parameters must be after the explicit setting of the System cpu list
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if fast_forward:
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shader.cpu_pointer = future_cpu_list[0]
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dispatcher.cpu = future_cpu_list[0]
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else:
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shader.cpu_pointer = host_cpu
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dispatcher.cpu = host_cpu
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dispatcher.shader_pointer = shader
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dispatcher.cl_driver = driver
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########################## Start simulation ########################
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root = Root(system=system, full_system=False)
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m5.ticks.setGlobalFrequency('1THz')
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if options.abs_max_tick:
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maxtick = options.abs_max_tick
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else:
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maxtick = m5.MaxTick
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# Benchmarks support work item annotations
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Simulation.setWorkCountOptions(system, options)
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# Checkpointing is not supported by APU model
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if (options.checkpoint_dir != None or
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options.checkpoint_restore != None):
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fatal("Checkpointing not supported by apu model")
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checkpoint_dir = None
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m5.instantiate(checkpoint_dir)
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# Map workload to this address space
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host_cpu.workload[0].map(0x10000000, 0x200000000, 4096)
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if options.fast_forward:
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print "Switch at instruction count: %d" % \
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cpu_list[0].max_insts_any_thread
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exit_event = m5.simulate(maxtick)
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if options.fast_forward:
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if exit_event.getCause() == "a thread reached the max instruction count":
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m5.switchCpus(system, switch_cpu_list)
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print "Switched CPUS @ tick %s" % (m5.curTick())
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m5.stats.reset()
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exit_event = m5.simulate(maxtick - m5.curTick())
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elif options.fast_forward_pseudo_op:
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while exit_event.getCause() == "switchcpu":
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# If we are switching *to* kvm, then the current stats are meaningful
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# Note that we don't do any warmup by default
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if type(switch_cpu_list[0][0]) == FutureCpuClass:
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print "Dumping stats..."
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m5.stats.dump()
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m5.switchCpus(system, switch_cpu_list)
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print "Switched CPUS @ tick %s" % (m5.curTick())
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m5.stats.reset()
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# This lets us switch back and forth without keeping a counter
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switch_cpu_list = [(x[1], x[0]) for x in switch_cpu_list]
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exit_event = m5.simulate(maxtick - m5.curTick())
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print "Ticks:", m5.curTick()
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print 'Exiting because ', exit_event.getCause()
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sys.exit(exit_event.getCode())
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