gem5/configs/common
2012-02-26 15:33:07 -08:00
..
Benchmarks.py configs: fix minor config bugs posted on the mailing list 2012-02-12 17:18:53 -06:00
CacheConfig.py Script: Fix the scripts that use the num_cpus cache parameter 2012-02-14 12:11:18 -05:00
Caches.py O3: Remove hardcoded tgts_per_mshr in O3CPU.py. 2011-12-01 00:15:22 -08:00
cpu2000.py cpu2000: Add missing art benchmark to all 2012-01-09 18:08:20 -06:00
FSConfig.py Make the IO bridge accept address headed to all the local APICs. 2012-02-26 15:33:07 -08:00
O3_ARM_v7a.py prefetcher: Make prefetcher a sim object instead of it being a parameter on cache 2012-02-12 16:07:38 -06:00
Options.py configs: A more realistic configuration of an ARM-like processor 2012-01-26 14:53:48 -05:00
Simulation.py SE/FS: Get rid of FULL_SYSTEM in the configs directory 2012-01-28 07:24:50 -08:00
SysPaths.py make rcS files read from the m5 source directory, not /dist. 2006-11-08 14:10:25 -05:00