92c5a5c8cb
configs/common/FSConfig.py:
seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
Use instruction count from cpu rather than cycles because that is what legion does
we can change it back after were done with legion
src/base/bitfield.hh:
add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
change asserts of packet success to if panics wrapped with NDEBUG defines
so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
convert some tabs to spaces
src/python/m5/objects/T1000.py:
add more fake devices for each l1 bank and each memory controller
--HG--
extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
97 lines
3.1 KiB
C++
97 lines
3.1 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/** @file
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* Declaration of a fake device.
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*/
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#ifndef __ISA_FAKE_HH__
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#define __ISA_FAKE_HH__
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#include "base/range.hh"
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#include "dev/io_device.hh"
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#include "dev/alpha/tsunami.hh"
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#include "mem/packet.hh"
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#include <string>
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/**
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* IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and
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* rites. It is meant to be placed at an address range
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* so that an mcheck doesn't occur when an os probes a piece of hw
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* that doesn't exist (e.g. UARTs1-3), or catch requests in the memory system
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* that have no responders..
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*/
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class IsaFake : public BasicPioDevice
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{
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public:
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struct Params : public BasicPioDevice::Params
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{
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Addr pio_size;
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bool retBadAddr;
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bool updateData;
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uint8_t retData8;
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uint16_t retData16;
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uint32_t retData32;
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uint64_t retData64;
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std::string warnAccess;
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};
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protected:
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const Params *params() const { return (const Params*)_params; }
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uint8_t retData8;
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uint16_t retData16;
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uint32_t retData32;
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uint64_t retData64;
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public:
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/**
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* The constructor for Tsunmami Fake just registers itself with the MMU.
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* @param p params structure
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*/
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IsaFake(Params *p);
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/**
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* This read always returns -1.
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* @param pkt The memory request.
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* @param data Where to put the data.
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*/
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virtual Tick read(PacketPtr pkt);
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/**
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* All writes are simply ignored.
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* @param pkt The memory request.
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* @param data the data to not write.
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*/
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virtual Tick write(PacketPtr pkt);
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};
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#endif // __ISA_FAKE_HH__
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