589e13a23b
Renaming members of the Wavefront class in accordance with the style guide.
209 lines
7.2 KiB
C++
209 lines
7.2 KiB
C++
/*
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* Copyright (c) 2012-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Steve Reinhardt
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*/
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#include "arch/hsail/insts/decl.hh"
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#include "debug/GPUExec.hh"
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#include "gpu-compute/dispatcher.hh"
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#include "gpu-compute/simple_pool_manager.hh"
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namespace HsailISA
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{
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template<> const char *B1::label = "b1";
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template<> const char *B8::label = "b8";
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template<> const char *B16::label = "b16";
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template<> const char *B32::label = "b32";
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template<> const char *B64::label = "b64";
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template<> const char *S8::label = "s8";
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template<> const char *S16::label = "s16";
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template<> const char *S32::label = "s32";
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template<> const char *S64::label = "s64";
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template<> const char *U8::label = "u8";
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template<> const char *U16::label = "u16";
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template<> const char *U32::label = "u32";
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template<> const char *U64::label = "u64";
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template<> const char *F32::label = "f32";
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template<> const char *F64::label = "f64";
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const char*
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cmpOpToString(Brig::BrigCompareOperation cmpOp)
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{
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using namespace Brig;
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switch (cmpOp) {
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case BRIG_COMPARE_EQ:
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return "eq";
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case BRIG_COMPARE_NE:
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return "ne";
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case BRIG_COMPARE_LT:
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return "lt";
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case BRIG_COMPARE_LE:
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return "le";
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case BRIG_COMPARE_GT:
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return "gt";
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case BRIG_COMPARE_GE:
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return "ge";
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case BRIG_COMPARE_EQU:
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return "equ";
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case BRIG_COMPARE_NEU:
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return "neu";
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case BRIG_COMPARE_LTU:
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return "ltu";
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case BRIG_COMPARE_LEU:
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return "leu";
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case BRIG_COMPARE_GTU:
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return "gtu";
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case BRIG_COMPARE_GEU:
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return "geu";
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case BRIG_COMPARE_NUM:
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return "num";
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case BRIG_COMPARE_NAN:
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return "nan";
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case BRIG_COMPARE_SEQ:
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return "seq";
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case BRIG_COMPARE_SNE:
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return "sne";
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case BRIG_COMPARE_SLT:
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return "slt";
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case BRIG_COMPARE_SLE:
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return "sle";
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case BRIG_COMPARE_SGT:
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return "sgt";
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case BRIG_COMPARE_SGE:
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return "sge";
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case BRIG_COMPARE_SGEU:
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return "sgeu";
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case BRIG_COMPARE_SEQU:
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return "sequ";
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case BRIG_COMPARE_SNEU:
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return "sneu";
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case BRIG_COMPARE_SLTU:
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return "sltu";
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case BRIG_COMPARE_SLEU:
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return "sleu";
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case BRIG_COMPARE_SNUM:
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return "snum";
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case BRIG_COMPARE_SNAN:
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return "snan";
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case BRIG_COMPARE_SGTU:
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return "sgtu";
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default:
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return "unknown";
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}
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}
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void
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Ret::execute(GPUDynInstPtr gpuDynInst)
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{
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Wavefront *w = gpuDynInst->wavefront();
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const VectorMask &mask = w->getPred();
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// mask off completed work-items
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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w->initMask[lane] = 0;
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}
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}
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// delete extra instructions fetched for completed work-items
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w->instructionBuffer.erase(w->instructionBuffer.begin() + 1,
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w->instructionBuffer.end());
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if (w->pendingFetch) {
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w->dropFetch = true;
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}
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// if all work-items have completed, then wave-front is done
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if (w->initMask.none()) {
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w->status = Wavefront::S_STOPPED;
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int32_t refCount = w->computeUnit->getLds().
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decreaseRefCounter(w->dispatchId, w->wgId);
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DPRINTF(GPUExec, "CU%d: decrease ref ctr WG[%d] to [%d]\n",
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w->computeUnit->cu_id, w->wgId, refCount);
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// free the vector registers of the completed wavefront
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w->computeUnit->vectorRegsReserved[w->simdId] -=
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w->reservedVectorRegs;
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assert(w->computeUnit->vectorRegsReserved[w->simdId] >= 0);
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uint32_t endIndex = (w->startVgprIndex +
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w->reservedVectorRegs - 1) %
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w->computeUnit->vrf[w->simdId]->numRegs();
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w->computeUnit->vrf[w->simdId]->manager->
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freeRegion(w->startVgprIndex, endIndex);
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w->reservedVectorRegs = 0;
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w->startVgprIndex = 0;
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w->computeUnit->completedWfs++;
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DPRINTF(GPUExec, "Doing return for CU%d: WF[%d][%d][%d]\n",
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w->computeUnit->cu_id, w->simdId, w->wfSlotId, w->wfDynId);
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if (!refCount) {
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// Notify Memory System of Kernel Completion
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// Kernel End = isKernel + isRelease
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w->status = Wavefront::S_RETURNING;
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GPUDynInstPtr local_mempacket = gpuDynInst;
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local_mempacket->memoryOrder = Enums::MEMORY_ORDER_SC_RELEASE;
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local_mempacket->scope = Enums::MEMORY_SCOPE_SYSTEM;
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local_mempacket->useContinuation = false;
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local_mempacket->simdId = w->simdId;
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local_mempacket->wfSlotId = w->wfSlotId;
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local_mempacket->wfDynId = w->wfDynId;
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w->computeUnit->injectGlobalMemFence(local_mempacket, true);
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} else {
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w->computeUnit->shader->dispatcher->scheduleDispatch();
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}
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}
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}
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void
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Barrier::execute(GPUDynInstPtr gpuDynInst)
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{
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Wavefront *w = gpuDynInst->wavefront();
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assert(w->barrierCnt == w->oldBarrierCnt);
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w->barrierCnt = w->oldBarrierCnt + 1;
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w->stalledAtBarrier = true;
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}
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} // namespace HsailISA
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