0dd1f7f01a
This reduces the scope of those includes and makes it less likely for there to be a dependency loop. This also moves the hashing functions associated with ExtMachInst objects to be with the ExtMachInst definitions and out of utility.hh.
153 lines
4.1 KiB
C++
153 lines
4.1 KiB
C++
/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include <cassert>
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#include "arch/alpha/isa.hh"
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#include "base/misc.hh"
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#include "cpu/thread_context.hh"
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#include "sim/serialize.hh"
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namespace AlphaISA
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{
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void
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ISA::serialize(EventManager *em, std::ostream &os)
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{
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SERIALIZE_SCALAR(fpcr);
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SERIALIZE_SCALAR(uniq);
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SERIALIZE_SCALAR(lock_flag);
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SERIALIZE_SCALAR(lock_addr);
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SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
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}
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void
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ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(fpcr);
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UNSERIALIZE_SCALAR(uniq);
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UNSERIALIZE_SCALAR(lock_flag);
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UNSERIALIZE_SCALAR(lock_addr);
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UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
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}
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MiscReg
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ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
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{
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switch (misc_reg) {
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case MISCREG_FPCR:
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return fpcr;
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case MISCREG_UNIQ:
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return uniq;
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case MISCREG_LOCKFLAG:
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return lock_flag;
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case MISCREG_LOCKADDR:
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return lock_addr;
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case MISCREG_INTR:
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return intr_flag;
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default:
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assert(misc_reg < NumInternalProcRegs);
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return ipr[misc_reg];
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}
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}
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MiscReg
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ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
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{
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switch (misc_reg) {
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case MISCREG_FPCR:
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return fpcr;
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case MISCREG_UNIQ:
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return uniq;
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case MISCREG_LOCKFLAG:
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return lock_flag;
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case MISCREG_LOCKADDR:
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return lock_addr;
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case MISCREG_INTR:
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return intr_flag;
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default:
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return readIpr(misc_reg, tc);
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}
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}
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void
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ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
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{
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switch (misc_reg) {
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case MISCREG_FPCR:
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fpcr = val;
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return;
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case MISCREG_UNIQ:
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uniq = val;
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return;
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case MISCREG_LOCKFLAG:
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lock_flag = val;
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return;
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case MISCREG_LOCKADDR:
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lock_addr = val;
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return;
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case MISCREG_INTR:
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intr_flag = val;
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return;
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default:
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assert(misc_reg < NumInternalProcRegs);
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ipr[misc_reg] = val;
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return;
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}
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}
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void
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ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
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ThreadID tid)
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{
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switch (misc_reg) {
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case MISCREG_FPCR:
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fpcr = val;
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return;
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case MISCREG_UNIQ:
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uniq = val;
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return;
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case MISCREG_LOCKFLAG:
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lock_flag = val;
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return;
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case MISCREG_LOCKADDR:
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lock_addr = val;
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return;
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case MISCREG_INTR:
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intr_flag = val;
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return;
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default:
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setIpr(misc_reg, val, tc);
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return;
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}
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}
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}
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