Kevin Lim bfa9cc2c3a Add some flags for the upcoming checker. ... arch/alpha/isa/decoder.isa: Mark store conditionals as serializing. This is slightly higher over head than they truly have in the 264, but it's close. Normally they block any other instructions from entering the IQ until the IQ is empty. This is higher overhead because it waits until the ROB is empty. Also mark RPCC as unverifiable. The checker will just grab the value from the instruction and assume it's correct. cpu/static_inst.hh: Add unverifiable flag, specifically for the CheckerCPU. --HG-- extra : convert_revision : cbc34d1f2f5b07105d31d4bd8f19edae2cf8158e		2006-05-16 13:48:05 -04:00
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alpha	Add some flags for the upcoming checker.	2006-05-16 13:48:05 -04:00
mips	last changes before big merge	2006-03-09 03:27:51 -05:00
sparc	fix merging issues	2006-03-09 16:17:10 -05:00
isa_parser.py	Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.	2006-03-03 15:28:25 -05:00
isa_specific.hh	Auto-generate arch/foo.hh "switch headers" in scons.	2006-02-22 22:22:06 -05:00
SConscript	Pushed ev5.hh out of the non-alpha code.	2006-03-07 14:08:01 -05:00