576196c13c
use quiesceNs on other CPUs
panic rather than spin on an error
console/Makefile:
Add m5op to the build process
console/dbmentry.S:
use quiesceNs on other CPUs
console/printf.c:
panic rather than spin on an error.
237 lines
7 KiB
ArmAsm
237 lines
7 KiB
ArmAsm
/*
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* Copyright (c) 2003, 2004
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* The Regents of The University of Michigan
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* All Rights Reserved
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*
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* This code is part of the M5 simulator, developed by Nathan Binkert,
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* Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
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* from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
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* Schultz.
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*
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* Permission is granted to use, copy, create derivative works and
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* redistribute this software and such derivative works for any purpose,
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* so long as the copyright notice above, this grant of permission, and
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* the disclaimer below appear in all copies made; and so long as the
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* name of The University of Michigan is not used in any advertising or
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* publicity pertaining to the use or distribution of this software
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* without specific, written prior authorization.
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*
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* THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
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* UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
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* WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
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* IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
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* THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
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* INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
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* DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
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* WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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*/
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/*
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* Copyright 1993 Hewlett-Packard Development Company, L.P.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/*
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* Debug Monitor Entry code
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*/
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#include "fromHudsonOsf.h"
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.extern myAlphaAccess
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.text
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/* return address and padding to octaword align */
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#define STARTFRM 16
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.globl _start
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.ent _start, 0
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_start:
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_entry:
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br t0, 2f # get the current PC
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2: ldgp gp, 0(t0) # init gp
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/* Processor 0 start stack frame is begining of physical memory (0)
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Other processors spin here waiting to get their stacks from
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Processor 0, then they can progress as normal.
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*/
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call_pal PAL_WHAMI_ENTRY
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beq v0, cpuz
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ldq t3, m5AlphaAccess
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addq t3,0x70,t3 # *** If offset in console alpha access struct changes
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# This must be changed as well!
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bis zero,8,t4
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mulq t4,v0,t4
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addq t3,t4,t3
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ldah a0, 3(zero) # load arg0 with 65536*3
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cpuwait: .long 0x6000002 # jsr quiesceNs
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ldq t4, 0(t3)
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beq t4, cpuwait
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bis t4,t4,sp
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cpuz: bis sp,sp,s0 /* save sp */
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slave: lda v0,(8*1024)(sp) /* end of page */
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subq zero, 1, t0
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sll t0, 42, t0
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bis t0, v0, sp
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lda sp, -STARTFRM(sp) # Create a stack frame
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stq ra, 0(sp) # Place return address on the stack
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.mask 0x84000000, -8
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.frame sp, STARTFRM, ra
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/*
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* Enable the Floating Point Unit
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*/
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lda a0, 1(zero)
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call_pal PAL_WRFEN_ENTRY
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/*
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* Every good C program has a main()
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*/
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/* If stack pointer was 0, then this is CPU0*/
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beq s0,master
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call_pal PAL_WHAMI_ENTRY
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bis v0,v0,a0
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jsr ra, SlaveLoop
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master:
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jsr ra, main
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/*
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* The Debug Monitor should never return.
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* However, just incase...
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*/
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ldgp gp, 0(ra)
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bsr zero, _exit
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.end _start
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.globl _exit
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.ent _exit, 0
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_exit:
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ldq ra, 0(sp) # restore return address
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lda sp, STARTFRM(sp) # prune back the stack
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ret zero, (ra) # Back from whence we came
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.end _exit
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.globl cServe
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.ent cServe 2
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cServe:
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.option O1
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.frame sp, 0, ra
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call_pal PAL_CSERVE_ENTRY
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ret zero, (ra)
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.end cServe
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.globl wrfen
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.ent wrfen 2
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wrfen:
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.option O1
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.frame sp, 0, ra
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call_pal PAL_WRFEN_ENTRY
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ret zero, (ra)
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.end wrfen
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.globl consoleCallback
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.ent consoleCallback 2
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consoleCallback:
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br t0, 2f # get the current PC
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2: ldgp gp, 0(t0) # init gp
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lda sp,-64(sp)
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stq ra,0(sp)
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jsr CallBackDispatcher
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ldq ra,0(sp)
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lda sp,64(sp)
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ret zero,(ra)
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.end consoleCallback
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.globl consoleFixup
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.ent consoleFixup 2
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consoleFixup:
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br t0, 2f # get the current PC
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2: ldgp gp, 0(t0) # init gp
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lda sp,-64(sp)
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stq ra,0(sp)
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jsr CallBackFixup
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ldq ra,0(sp)
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lda sp,64(sp)
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ret zero,(ra)
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.end consoleFixup
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.globl SpinLock
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.ent SpinLock 2
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SpinLock:
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1:
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ldq_l a1,0(a0) # interlock complete lock state
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subl ra,3,v0 # get calling addr[31:0] + 1
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blbs a1,2f # branch if lock is busy
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stq_c v0,0(a0) # attempt to acquire lock
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beq v0,2f # branch if lost atomicity
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mb # ensure memory coherence
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ret zero,(ra) # return to caller (v0 is 1)
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2:
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br zero,1b
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.end SpinLock
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.globl loadContext
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.ent loadContext 2
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loadContext:
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.option O1
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.frame sp, 0, ra
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call_pal PAL_SWPCTX_ENTRY
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ret zero, (ra)
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.end loadContext
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.globl SlaveSpin # Very carefully spin wait
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.ent SlaveSpin 2 # and swap context without
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SlaveSpin: # using any stack space
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.option O1
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.frame sp, 0, ra
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mov a0, t0 # cpu number
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mov a1, t1 # cpu rpb pointer (virtual)
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mov a2, t2 # what to spin on
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ldah a0, 3(zero) # load arg0 with 65536
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test: .long 0x6000002 # jsr quiesceNs # wait 65us*3
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ldl t3, 0(t2)
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beq t3, test
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zapnot t1,0x1f,a0 # make rpb physical
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call_pal PAL_SWPCTX_ENTRY # switch to pcb
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mov t0, a0 # setup args for SlaveCmd
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mov t1, a1
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jsr SlaveCmd # call SlaveCmd
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ret zero, (ra) # Should never be reached
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.end SlaveSpin
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