aefe9cc624
This patch adds the basic building blocks required to support e.g. ARM TrustZone by discerning secure and non-secure memory accesses.
322 lines
8.3 KiB
C++
322 lines
8.3 KiB
C++
/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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*/
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/**
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* @file
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* Definitions a fully associative LRU tagstore.
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*/
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#include <cassert>
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#include <sstream>
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#include "base/intmath.hh"
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#include "base/misc.hh"
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#include "mem/cache/tags/fa_lru.hh"
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using namespace std;
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FALRU::FALRU(const Params *p)
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: BaseTags(p)
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{
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if (!isPowerOf2(blkSize))
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fatal("cache block size (in bytes) `%d' must be a power of two",
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blkSize);
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if (!(hitLatency > 0))
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fatal("Access latency in cycles must be at least one cycle");
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if (!isPowerOf2(size))
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fatal("Cache Size must be power of 2 for now");
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// Track all cache sizes from 128K up by powers of 2
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numCaches = floorLog2(size) - 17;
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if (numCaches >0){
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cacheBoundaries = new FALRUBlk *[numCaches];
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cacheMask = (1 << numCaches) - 1;
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} else {
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cacheMask = 0;
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}
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warmedUp = false;
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warmupBound = size/blkSize;
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numBlocks = size/blkSize;
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blks = new FALRUBlk[numBlocks];
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head = &(blks[0]);
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tail = &(blks[numBlocks-1]);
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head->prev = NULL;
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head->next = &(blks[1]);
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head->inCache = cacheMask;
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tail->prev = &(blks[numBlocks-2]);
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tail->next = NULL;
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tail->inCache = 0;
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unsigned index = (1 << 17) / blkSize;
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unsigned j = 0;
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int flags = cacheMask;
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for (unsigned i = 1; i < numBlocks - 1; i++) {
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blks[i].inCache = flags;
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if (i == index - 1){
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cacheBoundaries[j] = &(blks[i]);
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flags &= ~ (1<<j);
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++j;
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index = index << 1;
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}
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blks[i].prev = &(blks[i-1]);
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blks[i].next = &(blks[i+1]);
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blks[i].isTouched = false;
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}
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assert(j == numCaches);
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assert(index == numBlocks);
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//assert(check());
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}
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FALRU::~FALRU()
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{
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if (numCaches)
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delete[] cacheBoundaries;
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delete[] blks;
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}
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void
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FALRU::regStats()
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{
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using namespace Stats;
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BaseTags::regStats();
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hits
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.init(numCaches+1)
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.name(name() + ".falru_hits")
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.desc("The number of hits in each cache size.")
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;
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misses
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.init(numCaches+1)
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.name(name() + ".falru_misses")
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.desc("The number of misses in each cache size.")
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;
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accesses
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.name(name() + ".falru_accesses")
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.desc("The number of accesses to the FA LRU cache.")
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;
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for (unsigned i = 0; i <= numCaches; ++i) {
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stringstream size_str;
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if (i < 3){
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size_str << (1<<(i+7)) <<"K";
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} else {
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size_str << (1<<(i-3)) <<"M";
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}
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hits.subname(i, size_str.str());
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hits.subdesc(i, "Hits in a " + size_str.str() +" cache");
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misses.subname(i, size_str.str());
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misses.subdesc(i, "Misses in a " + size_str.str() +" cache");
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}
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}
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FALRUBlk *
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FALRU::hashLookup(Addr addr) const
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{
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tagIterator iter = tagHash.find(addr);
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if (iter != tagHash.end()) {
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return (*iter).second;
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}
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return NULL;
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}
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void
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FALRU::invalidate(FALRU::BlkType *blk)
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{
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assert(blk);
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tagsInUse--;
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}
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FALRUBlk*
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FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src,
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int *inCache)
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{
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accesses++;
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int tmp_in_cache = 0;
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Addr blkAddr = blkAlign(addr);
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FALRUBlk* blk = hashLookup(blkAddr);
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if (blk && blk->isValid()) {
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assert(blk->tag == blkAddr);
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tmp_in_cache = blk->inCache;
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for (unsigned i = 0; i < numCaches; i++) {
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if (1<<i & blk->inCache) {
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hits[i]++;
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} else {
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misses[i]++;
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}
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}
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hits[numCaches]++;
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if (blk != head){
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moveToHead(blk);
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}
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} else {
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blk = NULL;
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for (unsigned i = 0; i <= numCaches; ++i) {
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misses[i]++;
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}
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}
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if (inCache) {
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*inCache = tmp_in_cache;
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}
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lat = hitLatency;
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//assert(check());
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return blk;
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}
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FALRUBlk*
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FALRU::findBlock(Addr addr, bool is_secure) const
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{
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Addr blkAddr = blkAlign(addr);
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FALRUBlk* blk = hashLookup(blkAddr);
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if (blk && blk->isValid()) {
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assert(blk->tag == blkAddr);
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} else {
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blk = NULL;
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}
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return blk;
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}
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FALRUBlk*
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FALRU::findVictim(Addr addr, PacketList &writebacks)
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{
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FALRUBlk * blk = tail;
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assert(blk->inCache == 0);
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moveToHead(blk);
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tagHash.erase(blk->tag);
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tagHash[blkAlign(addr)] = blk;
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if (blk->isValid()) {
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replacements[0]++;
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} else {
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tagsInUse++;
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blk->isTouched = true;
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if (!warmedUp && tagsInUse.value() >= warmupBound) {
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warmedUp = true;
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warmupCycle = curTick();
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}
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}
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//assert(check());
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return blk;
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}
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void
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FALRU::insertBlock(PacketPtr pkt, FALRU::BlkType *blk)
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{
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}
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void
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FALRU::moveToHead(FALRUBlk *blk)
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{
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int updateMask = blk->inCache ^ cacheMask;
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for (unsigned i = 0; i < numCaches; i++){
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if ((1<<i) & updateMask) {
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cacheBoundaries[i]->inCache &= ~(1<<i);
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cacheBoundaries[i] = cacheBoundaries[i]->prev;
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} else if (cacheBoundaries[i] == blk) {
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cacheBoundaries[i] = blk->prev;
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}
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}
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blk->inCache = cacheMask;
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if (blk != head) {
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if (blk == tail){
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assert(blk->next == NULL);
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tail = blk->prev;
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tail->next = NULL;
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} else {
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blk->prev->next = blk->next;
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blk->next->prev = blk->prev;
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}
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blk->next = head;
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blk->prev = NULL;
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head->prev = blk;
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head = blk;
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}
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}
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bool
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FALRU::check()
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{
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FALRUBlk* blk = head;
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int tot_size = 0;
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int boundary = 1<<17;
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int j = 0;
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int flags = cacheMask;
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while (blk) {
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tot_size += blkSize;
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if (blk->inCache != flags) {
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return false;
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}
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if (tot_size == boundary && blk != tail) {
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if (cacheBoundaries[j] != blk) {
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return false;
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}
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flags &=~(1 << j);
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boundary = boundary<<1;
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++j;
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}
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blk = blk->next;
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}
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return true;
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}
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void
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FALRU::clearLocks()
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{
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for (int i = 0; i < numBlocks; i++){
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blks[i].clearLoadLocks();
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}
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}
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FALRU *
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FALRUParams::create()
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{
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return new FALRU(this);
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}
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