f0fb3ac060
Make interrupts use the new wakeup method, and pull all of the interrupt stuff into the cpu base class so that only the wakeup code needs to be updated. I tried to make wakeup, wakeCPU, and the various other mechanisms for waking and sleeping a little more sane, but I couldn't understand why the statistics were changing the way they were. Maybe we'll try again some day.
310 lines
8.6 KiB
C++
310 lines
8.6 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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*/
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#ifndef __CPU_BASE_HH__
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#define __CPU_BASE_HH__
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#include <vector>
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#include "arch/isa_traits.hh"
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#include "arch/microcode_rom.hh"
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#include "base/statistics.hh"
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#include "config/full_system.hh"
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#include "sim/eventq.hh"
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#include "sim/insttracer.hh"
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#include "mem/mem_object.hh"
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#if FULL_SYSTEM
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#include "arch/interrupts.hh"
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#endif
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class BaseCPUParams;
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class BranchPred;
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class CheckerCPU;
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class ThreadContext;
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class System;
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class Port;
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namespace TheISA
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{
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class Predecoder;
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}
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class CPUProgressEvent : public Event
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{
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protected:
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Tick interval;
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Counter lastNumInst;
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BaseCPU *cpu;
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public:
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CPUProgressEvent(BaseCPU *_cpu, Tick ival);
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void process();
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virtual const char *description() const;
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};
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class BaseCPU : public MemObject
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{
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protected:
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// CPU's clock period in terms of the number of ticks of curTime.
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Tick clock;
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// @todo remove me after debugging with legion done
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Tick instCnt;
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// every cpu has an id, put it in the base cpu
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// Set at initialization, only time a cpuId might change is during a
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// takeover (which should be done from within the BaseCPU anyway,
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// therefore no setCpuId() method is provided
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int _cpuId;
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public:
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/** Reads this CPU's ID. */
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int cpuId() { return _cpuId; }
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// Tick currentTick;
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inline Tick frequency() const { return Clock::Frequency / clock; }
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inline Tick ticks(int numCycles) const { return clock * numCycles; }
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inline Tick curCycle() const { return curTick / clock; }
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inline Tick tickToCycles(Tick val) const { return val / clock; }
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// @todo remove me after debugging with legion done
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Tick instCount() { return instCnt; }
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/** The next cycle the CPU should be scheduled, given a cache
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* access or quiesce event returning on this cycle. This function
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* may return curTick if the CPU should run on the current cycle.
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*/
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Tick nextCycle();
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/** The next cycle the CPU should be scheduled, given a cache
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* access or quiesce event returning on the given Tick. This
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* function may return curTick if the CPU should run on the
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* current cycle.
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* @param begin_tick The tick that the event is completing on.
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*/
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Tick nextCycle(Tick begin_tick);
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TheISA::MicrocodeRom microcodeRom;
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#if FULL_SYSTEM
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protected:
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TheISA::Interrupts *interrupts;
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public:
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TheISA::Interrupts *
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getInterruptController()
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{
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return interrupts;
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}
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virtual void wakeup() = 0;
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void
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postInterrupt(int int_num, int index)
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{
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interrupts->post(int_num, index);
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wakeup();
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}
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void
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clearInterrupt(int int_num, int index)
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{
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interrupts->clear(int_num, index);
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}
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void
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clearInterrupts()
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{
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interrupts->clearAll();
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}
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bool
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checkInterrupts(ThreadContext *tc) const
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{
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return interrupts->checkInterrupts(tc);
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}
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class ProfileEvent : public Event
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{
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private:
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BaseCPU *cpu;
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Tick interval;
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public:
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ProfileEvent(BaseCPU *cpu, Tick interval);
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void process();
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};
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ProfileEvent *profileEvent;
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#endif
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protected:
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std::vector<ThreadContext *> threadContexts;
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std::vector<TheISA::Predecoder *> predecoders;
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Trace::InstTracer * tracer;
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public:
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/// Provide access to the tracer pointer
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Trace::InstTracer * getTracer() { return tracer; }
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/// Notify the CPU that the indicated context is now active. The
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/// delay parameter indicates the number of ticks to wait before
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/// executing (typically 0 or 1).
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virtual void activateContext(int thread_num, int delay) {}
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/// Notify the CPU that the indicated context is now suspended.
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virtual void suspendContext(int thread_num) {}
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/// Notify the CPU that the indicated context is now deallocated.
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virtual void deallocateContext(int thread_num) {}
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/// Notify the CPU that the indicated context is now halted.
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virtual void haltContext(int thread_num) {}
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/// Given a Thread Context pointer return the thread num
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int findContext(ThreadContext *tc);
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/// Given a thread num get tho thread context for it
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ThreadContext *getContext(int tn) { return threadContexts[tn]; }
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public:
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typedef BaseCPUParams Params;
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const Params *params() const
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{ return reinterpret_cast<const Params *>(_params); }
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BaseCPU(Params *params);
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virtual ~BaseCPU();
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virtual void init();
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virtual void startup();
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virtual void regStats();
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virtual void activateWhenReady(int tid) {};
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void registerThreadContexts();
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/// Prepare for another CPU to take over execution. When it is
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/// is ready (drained pipe) it signals the sampler.
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virtual void switchOut();
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/// Take over execution from the given CPU. Used for warm-up and
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/// sampling.
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virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
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/**
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* Number of threads we're actually simulating (<= SMT_MAX_THREADS).
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* This is a constant for the duration of the simulation.
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*/
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int number_of_threads;
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TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
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/**
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* Vector of per-thread instruction-based event queues. Used for
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* scheduling events based on number of instructions committed by
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* a particular thread.
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*/
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EventQueue **comInstEventQueue;
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/**
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* Vector of per-thread load-based event queues. Used for
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* scheduling events based on number of loads committed by
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*a particular thread.
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*/
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EventQueue **comLoadEventQueue;
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System *system;
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Tick phase;
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#if FULL_SYSTEM
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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#endif
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/**
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* Return pointer to CPU's branch predictor (NULL if none).
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* @return Branch predictor pointer.
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*/
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virtual BranchPred *getBranchPred() { return NULL; };
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virtual Counter totalInstructions() const { return 0; }
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// Function tracing
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private:
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bool functionTracingEnabled;
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std::ostream *functionTraceStream;
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Addr currentFunctionStart;
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Addr currentFunctionEnd;
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Tick functionEntryTick;
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void enableFunctionTrace();
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void traceFunctionsInternal(Addr pc);
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protected:
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void traceFunctions(Addr pc)
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{
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if (functionTracingEnabled)
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traceFunctionsInternal(pc);
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}
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private:
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static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
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public:
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static int numSimulatedCPUs() { return cpuList.size(); }
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static Counter numSimulatedInstructions()
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{
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Counter total = 0;
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int size = cpuList.size();
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for (int i = 0; i < size; ++i)
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total += cpuList[i]->totalInstructions();
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return total;
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}
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public:
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// Number of CPU cycles simulated
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Stats::Scalar<> numCycles;
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};
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#endif // __CPU_BASE_HH__
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