9d39407500
tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr:
tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr:
tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout:
tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini:
tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out:
tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr:
tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout:
tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini:
tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out:
tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr:
tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout:
tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini:
tests/long/30.eon/ref/alpha/linux/simple-timing/config.out:
tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/linux/simple-timing/stderr:
tests/long/30.eon/ref/alpha/linux/simple-timing/stdout:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr:
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout:
tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr:
tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr:
tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout:
tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini:
tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out:
tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr:
tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr:
tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr:
tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr:
tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout:
tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr:
tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr:
tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout:
tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini:
tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out:
tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr:
tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout:
Update with actual benchmark output.
--HG--
extra : convert_revision : 12e8de58172dd717d9cc8c5c27dd926a7257153c
418 lines
45 KiB
Plaintext
418 lines
45 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 13144986 # Number of BTB hits
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global.BPredUnit.BTBLookups 21876990 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 30485 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 454636 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 16268422 # Number of conditional branches predicted
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global.BPredUnit.lookups 26797394 # Number of BP lookups
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global.BPredUnit.usedRAS 4858022 # Number of times the RAS was used to get a target.
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host_inst_rate 52852 # Simulator instruction rate (inst/s)
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host_mem_usage 259420 # Number of bytes of host memory used
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host_seconds 1506.34 # Real time elapsed on the host
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host_tick_rate 744190 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 14725219 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 11320400 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 28503669 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 16218894 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 79613339 # Number of instructions simulated
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sim_seconds 0.001121 # Number of seconds simulated
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sim_ticks 1121005014 # Number of ticks simulated
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system.cpu.commit.COM:branches 13759853 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 3902181 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 88439527
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 61749847 6982.15%
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1 8803671 995.45%
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2 5177009 585.37%
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3 3274877 370.30%
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4 2188473 247.45%
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5 1421818 160.77%
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6 1152410 130.30%
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7 769241 86.98%
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8 3902181 441.23%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 88361897 # Number of instructions committed
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system.cpu.commit.COM:loads 20383045 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 35229375 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 360073 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 88361897 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 4706 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 20725845 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 79613339 # Number of Instructions Simulated
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system.cpu.committedInsts_total 79613339 # Number of Instructions Simulated
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system.cpu.cpi 14.080618 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 14.080618 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 19542402 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 4437.586724 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3280.646620 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 19388897 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 681191750 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.007855 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 153505 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 94427 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 193814041 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.003023 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 59078 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 4852.594089 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4028.169523 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 13950409 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 3228304680 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.045518 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 665274 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 523305 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 571875199 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.009713 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 141969 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 3068.165217 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 3779.642588 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 165.828418 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 115 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 125189 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 352839 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 473169676 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 34158085 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 4774.788349 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 3808.508657 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 33339306 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 3909496430 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.023970 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 818779 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 617732 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 765689240 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.005886 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 201047 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 34158085 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 4774.788349 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 3808.508657 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 33339306 # number of overall hits
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system.cpu.dcache.overall_miss_latency 3909496430 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.023970 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 818779 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 617732 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 765689240 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.005886 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 201047 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 196951 # number of replacements
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system.cpu.dcache.sampled_refs 201047 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4057.206862 # Cycle average of tags in use
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system.cpu.dcache.total_refs 33339306 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 27763000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 147199 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 11824495 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 95570 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 3548160 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 129766996 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 51039022 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 25179247 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 4520828 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 280755 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 396764 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 26797394 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 22435045 # Number of cache lines fetched
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system.cpu.fetch.Cycles 50869599 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 152238 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 146401648 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 3850495 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.288267 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 22435045 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 18003008 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.574883 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 92960356
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system.cpu.fetch.rateDist.min_value 0
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0 64525729 6941.21%
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1 1650999 177.60%
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2 1736489 186.80%
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3 1914591 205.96%
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4 6963270 749.06%
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5 6073717 653.37%
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6 756313 81.36%
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7 1939629 208.65%
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8 7399619 796.00%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 22435044 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 3343.146524 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 2355.643274 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 22333491 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 339506559 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.004527 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 101553 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 13791 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 206735965 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.003912 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 87762 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets 3964.923913 # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 254.480817 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 92 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 364773 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 22435044 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 3343.146524 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 2355.643274 # average overall mshr miss latency
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system.cpu.icache.demand_hits 22333491 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 339506559 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.004527 # miss rate for demand accesses
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system.cpu.icache.demand_misses 101553 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 13791 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 206735965 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.003912 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 87762 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 22435044 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 3343.146524 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 2355.643274 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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|
system.cpu.icache.overall_hits 22333491 # number of overall hits
|
|
system.cpu.icache.overall_miss_latency 339506559 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_rate 0.004527 # miss rate for overall accesses
|
|
system.cpu.icache.overall_misses 101553 # number of overall misses
|
|
system.cpu.icache.overall_mshr_hits 13791 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_miss_latency 206735965 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_rate 0.003912 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_misses 87762 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.icache.replacements 85714 # number of replacements
|
|
system.cpu.icache.sampled_refs 87761 # Sample count of references to valid blocks.
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.tagsinuse 1835.660061 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 22333491 # Total number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
system.cpu.idleCycles 1028044659 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.iew.EXEC:branches 14368697 # Number of branches executed
|
|
system.cpu.iew.EXEC:nop 9207761 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 0.998957 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs 42889191 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores 15296362 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 46149810 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 85978243 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 0.741638 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 34226464 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 0.924891 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 86043563 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 388948 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 3476074 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 28503669 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 5221 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 1221579 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 16218894 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 109084579 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 27592829 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 454683 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 92863355 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 28537 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 13436 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 4520828 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 193035 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 1537 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 6697780 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 1365345 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 4018 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 3952 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1537 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 8120624 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 1372564 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 3952 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 217352 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 171596 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.071020 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.071020 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 93318038 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
(null) 0 0.00% # Type of FU issued
|
|
IntAlu 49917747 53.49% # Type of FU issued
|
|
IntMult 43212 0.05% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 123778 0.13% # Type of FU issued
|
|
FloatCmp 88 0.00% # Type of FU issued
|
|
FloatCvt 122460 0.13% # Type of FU issued
|
|
FloatMult 54 0.00% # Type of FU issued
|
|
FloatDiv 37863 0.04% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 27694961 29.68% # Type of FU issued
|
|
MemWrite 15377875 16.48% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 1239796 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.013286 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
(null) 0 0.00% # attempts to use FU when none available
|
|
IntAlu 81158 6.55% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 587235 47.37% # attempts to use FU when none available
|
|
MemWrite 571403 46.09% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 92960356
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 53328498 5736.69%
|
|
1 13184129 1418.25%
|
|
2 10577669 1137.87%
|
|
3 8760562 942.40%
|
|
4 4405028 473.86%
|
|
5 1612052 173.41%
|
|
6 698100 75.10%
|
|
7 326631 35.14%
|
|
8 67687 7.28%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 1.003848 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 99871597 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 93318038 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 5221 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 20057396 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 77651 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 15480029 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.l2cache.ReadReq_accesses 288801 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 3932.513738 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2042.965502 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 119343 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 666395913 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.586764 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 169458 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 346196848 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.586764 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 169458 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147199 # number of WriteReqNoAck|Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146588 # number of WriteReqNoAck|Writeback hits
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.004151 # miss rate for WriteReqNoAck|Writeback accesses
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_misses 611 # number of WriteReqNoAck|Writeback misses
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.004151 # mshr miss rate for WriteReqNoAck|Writeback accesses
|
|
system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 611 # number of WriteReqNoAck|Writeback MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 1.569313 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 288801 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 3932.513738 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2042.965502 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 119343 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 666395913 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.586764 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 169458 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 346196848 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.586764 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 169458 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 436000 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 3918.385555 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2042.965502 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 265931 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 666395913 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.390067 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 170069 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 346196848 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.388665 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 169458 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 136689 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 169457 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 30306.924097 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 265931 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 442261000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 115687 # number of writebacks
|
|
system.cpu.numCycles 92960356 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 7634208 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 52562815 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 86713 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 51709233 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 3226687 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 2442 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 152860701 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 128373944 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 81757058 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 24895195 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 4520828 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 3457989 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 29194243 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 742903 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 5237 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 6117149 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 5235 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 271656 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|