422 lines
13 KiB
C++
422 lines
13 KiB
C++
/*
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* Copyright (c) 2008 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use of this software in source and binary forms,
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* with or without modification, are permitted provided that the
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* following conditions are met:
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*
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* The software must be used only for Non-Commercial Use which means any
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* use which is NOT directed to receiving any direct monetary
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* compensation for, or commercial advantage from such use. Illustrative
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* examples of non-commercial use are academic research, personal study,
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* teaching, education and corporate research & development.
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* Illustrative examples of commercial use are distributing products for
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* commercial advantage and providing services using the software for
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* commercial advantage.
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*
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* If you wish to use this software or functionality therein that may be
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* covered by patents for commercial use, please contact:
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* Director of Intellectual Property Licensing
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* Office of Strategy and Technology
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* Hewlett-Packard Company
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* 1501 Page Mill Road
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* Palo Alto, California 94304
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*
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* Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer. Redistributions
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* in binary form must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution. Neither the name of
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* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission. No right of
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* sublicense is granted herewith. Derivatives of the software and
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* output created using the software may be prepared, but only for
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* Non-Commercial Uses. Derivatives of the software may be shared with
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* others provided: (i) the others agree to abide by the list of
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* conditions herein which includes the Non-Commercial Use restrictions;
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* and (ii) such Derivatives of the software include the above copyright
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* notice to acknowledge the contribution from this software where
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* applicable, this list of conditions and the disclaimer below.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/apicregs.hh"
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#include "arch/x86/interrupts.hh"
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#include "cpu/base.hh"
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int
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divideFromConf(uint32_t conf)
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{
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// This figures out what division we want from the division configuration
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// register in the local APIC. The encoding is a little odd but it can
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// be deciphered fairly easily.
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int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
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shift = (shift + 1) % 8;
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return 1 << shift;
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}
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namespace X86ISA
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{
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ApicRegIndex
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decodeAddr(Addr paddr)
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{
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ApicRegIndex regNum;
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paddr &= ~mask(3);
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switch (paddr)
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{
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case 0x20:
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regNum = APIC_ID;
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break;
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case 0x30:
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regNum = APIC_VERSION;
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break;
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case 0x80:
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regNum = APIC_TASK_PRIORITY;
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break;
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case 0x90:
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regNum = APIC_ARBITRATION_PRIORITY;
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break;
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case 0xA0:
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regNum = APIC_PROCESSOR_PRIORITY;
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break;
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case 0xB0:
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regNum = APIC_EOI;
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break;
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case 0xD0:
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regNum = APIC_LOGICAL_DESTINATION;
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break;
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case 0xE0:
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regNum = APIC_DESTINATION_FORMAT;
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break;
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case 0xF0:
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regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
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break;
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case 0x100:
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case 0x108:
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case 0x110:
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case 0x118:
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case 0x120:
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case 0x128:
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case 0x130:
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case 0x138:
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case 0x140:
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case 0x148:
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case 0x150:
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case 0x158:
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case 0x160:
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case 0x168:
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case 0x170:
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case 0x178:
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regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
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break;
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case 0x180:
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case 0x188:
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case 0x190:
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case 0x198:
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case 0x1A0:
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case 0x1A8:
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case 0x1B0:
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case 0x1B8:
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case 0x1C0:
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case 0x1C8:
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case 0x1D0:
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case 0x1D8:
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case 0x1E0:
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case 0x1E8:
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case 0x1F0:
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case 0x1F8:
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regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
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break;
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case 0x200:
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case 0x208:
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case 0x210:
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case 0x218:
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case 0x220:
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case 0x228:
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case 0x230:
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case 0x238:
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case 0x240:
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case 0x248:
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case 0x250:
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case 0x258:
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case 0x260:
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case 0x268:
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case 0x270:
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case 0x278:
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regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
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break;
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case 0x280:
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regNum = APIC_ERROR_STATUS;
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break;
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case 0x300:
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regNum = APIC_INTERRUPT_COMMAND_LOW;
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break;
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case 0x310:
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regNum = APIC_INTERRUPT_COMMAND_HIGH;
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break;
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case 0x320:
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regNum = APIC_LVT_TIMER;
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break;
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case 0x330:
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regNum = APIC_LVT_THERMAL_SENSOR;
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break;
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case 0x340:
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regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
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break;
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case 0x350:
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regNum = APIC_LVT_LINT0;
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break;
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case 0x360:
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regNum = APIC_LVT_LINT1;
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break;
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case 0x370:
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regNum = APIC_LVT_ERROR;
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break;
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case 0x380:
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regNum = APIC_INITIAL_COUNT;
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break;
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case 0x390:
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regNum = APIC_CURRENT_COUNT;
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break;
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case 0x3E0:
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regNum = APIC_DIVIDE_CONFIGURATION;
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break;
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default:
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// A reserved register field.
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panic("Accessed reserved register field %#x.\n", paddr);
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break;
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}
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return regNum;
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}
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}
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Tick
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X86ISA::Interrupts::read(PacketPtr pkt)
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{
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Addr offset = pkt->getAddr() - pioAddr;
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//Make sure we're at least only accessing one register.
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if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
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panic("Accessed more than one register at a time in the APIC!\n");
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ApicRegIndex reg = decodeAddr(offset);
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uint32_t val = htog(readReg(reg));
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DPRINTF(LocalApic,
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"Reading Local APIC register %d at offset %#x as %#x.\n",
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reg, offset, val);
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pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
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return latency;
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}
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Tick
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X86ISA::Interrupts::write(PacketPtr pkt)
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{
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Addr offset = pkt->getAddr() - pioAddr;
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//Make sure we're at least only accessing one register.
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if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
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panic("Accessed more than one register at a time in the APIC!\n");
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ApicRegIndex reg = decodeAddr(offset);
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uint32_t val = regs[reg];
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pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
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DPRINTF(LocalApic,
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"Writing Local APIC register %d at offset %#x as %#x.\n",
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reg, offset, gtoh(val));
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setReg(reg, gtoh(val));
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return latency;
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}
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Tick
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X86ISA::Interrupts::recvMessage(PacketPtr pkt)
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{
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Addr offset = pkt->getAddr() - x86InterruptAddress(0, 0);
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assert(pkt->cmd == MemCmd::MessageReq);
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switch(offset)
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{
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case 0:
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DPRINTF(LocalApic, "Got Trigger Interrupt message.\n");
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break;
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default:
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panic("Local apic got unknown interrupt message at offset %#x.\n",
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offset);
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break;
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}
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delete pkt->req;
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delete pkt;
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return latency;
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}
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uint32_t
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X86ISA::Interrupts::readReg(ApicRegIndex reg)
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{
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if (reg >= APIC_TRIGGER_MODE(0) &&
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reg <= APIC_TRIGGER_MODE(15)) {
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panic("Local APIC Trigger Mode registers are unimplemented.\n");
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}
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switch (reg) {
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case APIC_ARBITRATION_PRIORITY:
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panic("Local APIC Arbitration Priority register unimplemented.\n");
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break;
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case APIC_PROCESSOR_PRIORITY:
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panic("Local APIC Processor Priority register unimplemented.\n");
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break;
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case APIC_EOI:
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panic("Local APIC EOI register unimplemented.\n");
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break;
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case APIC_ERROR_STATUS:
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regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
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break;
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case APIC_INTERRUPT_COMMAND_LOW:
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panic("Local APIC Interrupt Command low"
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" register unimplemented.\n");
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break;
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case APIC_INTERRUPT_COMMAND_HIGH:
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panic("Local APIC Interrupt Command high"
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" register unimplemented.\n");
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break;
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case APIC_CURRENT_COUNT:
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{
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assert(clock);
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uint32_t val = regs[reg] - curTick / clock;
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val /= (16 * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
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return val;
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}
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default:
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break;
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}
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return regs[reg];
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}
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void
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X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
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{
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uint32_t newVal = val;
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if (reg >= APIC_IN_SERVICE(0) &&
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reg <= APIC_IN_SERVICE(15)) {
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panic("Local APIC In-Service registers are unimplemented.\n");
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}
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if (reg >= APIC_TRIGGER_MODE(0) &&
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reg <= APIC_TRIGGER_MODE(15)) {
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panic("Local APIC Trigger Mode registers are unimplemented.\n");
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}
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if (reg >= APIC_INTERRUPT_REQUEST(0) &&
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reg <= APIC_INTERRUPT_REQUEST(15)) {
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panic("Local APIC Interrupt Request registers "
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"are unimplemented.\n");
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}
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switch (reg) {
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case APIC_ID:
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newVal = val & 0xFF;
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break;
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case APIC_VERSION:
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// The Local APIC Version register is read only.
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return;
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case APIC_TASK_PRIORITY:
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newVal = val & 0xFF;
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break;
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case APIC_ARBITRATION_PRIORITY:
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panic("Local APIC Arbitration Priority register unimplemented.\n");
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break;
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case APIC_PROCESSOR_PRIORITY:
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panic("Local APIC Processor Priority register unimplemented.\n");
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break;
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case APIC_EOI:
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panic("Local APIC EOI register unimplemented.\n");
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break;
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case APIC_LOGICAL_DESTINATION:
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newVal = val & 0xFF000000;
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break;
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case APIC_DESTINATION_FORMAT:
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newVal = val | 0x0FFFFFFF;
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break;
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case APIC_SPURIOUS_INTERRUPT_VECTOR:
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regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
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regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
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if (val & (1 << 9))
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warn("Focus processor checking not implemented.\n");
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break;
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case APIC_ERROR_STATUS:
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{
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if (regs[APIC_INTERNAL_STATE] & 0x1) {
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regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
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newVal = 0;
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} else {
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regs[APIC_INTERNAL_STATE] |= ULL(0x1);
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return;
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}
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}
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break;
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case APIC_INTERRUPT_COMMAND_LOW:
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panic("Local APIC Interrupt Command low"
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" register unimplemented.\n");
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break;
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case APIC_INTERRUPT_COMMAND_HIGH:
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panic("Local APIC Interrupt Command high"
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" register unimplemented.\n");
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break;
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case APIC_LVT_TIMER:
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case APIC_LVT_THERMAL_SENSOR:
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case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
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case APIC_LVT_LINT0:
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case APIC_LVT_LINT1:
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case APIC_LVT_ERROR:
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{
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uint64_t readOnlyMask = (1 << 12) | (1 << 14);
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newVal = (val & ~readOnlyMask) |
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(regs[reg] & readOnlyMask);
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}
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break;
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case APIC_INITIAL_COUNT:
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{
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assert(clock);
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newVal = bits(val, 31, 0);
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uint32_t newCount = newVal *
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(divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]) * 16);
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regs[APIC_CURRENT_COUNT] = newCount + curTick / clock;
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// Find out how long a "tick" of the timer should take.
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Tick timerTick = 16 * clock;
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// Schedule on the edge of the next tick plus the new count.
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Tick offset = curTick % timerTick;
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if (offset) {
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reschedule(apicTimerEvent,
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curTick + (newCount + 1) * timerTick - offset, true);
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} else {
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reschedule(apicTimerEvent,
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curTick + newCount * timerTick, true);
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}
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}
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break;
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case APIC_CURRENT_COUNT:
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//Local APIC Current Count register is read only.
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return;
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case APIC_DIVIDE_CONFIGURATION:
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newVal = val & 0xB;
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break;
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default:
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break;
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}
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regs[reg] = newVal;
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return;
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}
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X86ISA::Interrupts *
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X86LocalApicParams::create()
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{
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return new X86ISA::Interrupts(this);
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}
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