610 lines
68 KiB
Text
610 lines
68 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.915549 # Number of seconds simulated
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sim_ticks 1915548867000 # Number of ticks simulated
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final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1998214 # Simulator instruction rate (inst/s)
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host_op_rate 1998212 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 68184353129 # Simulator tick rate (ticks/s)
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host_mem_usage 288188 # Number of bytes of host memory used
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host_seconds 28.09 # Real time elapsed on the host
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sim_insts 56137087 # Number of instructions simulated
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sim_ops 56137087 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 29663360 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 10122368 # Number of bytes written to this memory
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system.physmem.num_reads 463490 # Number of read requests responded to by this memory
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system.physmem.num_writes 158162 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 15485567 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 492308 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 5284317 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 20769884 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.replacements 389289 # number of replacements
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system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use
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system.l2c.total_refs 2311163 # Total number of references to valid blocks.
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system.l2c.sampled_refs 421794 # Sample count of references to valid blocks.
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system.l2c.avg_refs 5.479364 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::writebacks 23110.665097 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu.inst 3746.363547 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu.data 7495.009700 # Average occupied blocks per requestor
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system.l2c.occ_percent::writebacks 0.352641 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu.inst 0.057165 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu.data 0.114365 # Average percentage of cache occupancy
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system.l2c.occ_percent::total 0.524171 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::cpu.inst 913599 # number of ReadReq hits
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system.l2c.ReadReq_hits::cpu.data 796862 # number of ReadReq hits
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system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits
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system.l2c.Writeback_hits::writebacks 826671 # number of Writeback hits
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system.l2c.Writeback_hits::total 826671 # number of Writeback hits
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system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits
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system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits
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system.l2c.ReadExReq_hits::cpu.data 185878 # number of ReadExReq hits
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system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits
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system.l2c.demand_hits::cpu.inst 913599 # number of demand (read+write) hits
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system.l2c.demand_hits::cpu.data 982740 # number of demand (read+write) hits
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system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits
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system.l2c.overall_hits::cpu.inst 913599 # number of overall hits
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system.l2c.overall_hits::cpu.data 982740 # number of overall hits
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system.l2c.overall_hits::total 1896339 # number of overall hits
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system.l2c.ReadReq_misses::cpu.inst 14735 # number of ReadReq misses
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system.l2c.ReadReq_misses::cpu.data 289403 # number of ReadReq misses
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system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses
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system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses
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system.l2c.ReadExReq_misses::cpu.data 118294 # number of ReadExReq misses
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system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses
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system.l2c.demand_misses::cpu.inst 14735 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu.data 407697 # number of demand (read+write) misses
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system.l2c.demand_misses::total 422432 # number of demand (read+write) misses
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system.l2c.overall_misses::cpu.inst 14735 # number of overall misses
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system.l2c.overall_misses::cpu.data 407697 # number of overall misses
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system.l2c.overall_misses::total 422432 # number of overall misses
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system.l2c.ReadReq_miss_latency::cpu.inst 766261500 # number of ReadReq miss cycles
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system.l2c.ReadReq_miss_latency::cpu.data 15053945000 # number of ReadReq miss cycles
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system.l2c.ReadReq_miss_latency::total 15820206500 # number of ReadReq miss cycles
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system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles
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system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles
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system.l2c.ReadExReq_miss_latency::cpu.data 6151753000 # number of ReadExReq miss cycles
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system.l2c.ReadExReq_miss_latency::total 6151753000 # number of ReadExReq miss cycles
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system.l2c.demand_miss_latency::cpu.inst 766261500 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::cpu.data 21205698000 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::total 21971959500 # number of demand (read+write) miss cycles
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system.l2c.overall_miss_latency::cpu.inst 766261500 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu.data 21205698000 # number of overall miss cycles
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system.l2c.overall_miss_latency::total 21971959500 # number of overall miss cycles
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system.l2c.ReadReq_accesses::cpu.inst 928334 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu.data 1086265 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses)
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system.l2c.Writeback_accesses::writebacks 826671 # number of Writeback accesses(hits+misses)
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system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
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system.l2c.demand_accesses::cpu.inst 928334 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu.data 1390437 # number of demand (read+write) accesses
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system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses
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system.l2c.overall_accesses::cpu.inst 928334 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu.data 1390437 # number of overall (read+write) accesses
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system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses
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system.l2c.ReadReq_miss_rate::cpu.inst 0.015873 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::cpu.data 0.266420 # miss rate for ReadReq accesses
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system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_miss_rate::cpu.data 0.388905 # miss rate for ReadExReq accesses
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system.l2c.demand_miss_rate::cpu.inst 0.015873 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu.data 0.293215 # miss rate for demand accesses
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system.l2c.overall_miss_rate::cpu.inst 0.015873 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu.data 0.293215 # miss rate for overall accesses
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system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937 # average ReadReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884 # average ReadExReq miss latency
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system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
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system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.l2c.fast_writes 0 # number of fast writes performed
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system.l2c.cache_copies 0 # number of cache copies performed
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system.l2c.writebacks::writebacks 116650 # number of writebacks
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system.l2c.writebacks::total 116650 # number of writebacks
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system.l2c.ReadReq_mshr_misses::cpu.inst 14735 # number of ReadReq MSHR misses
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system.l2c.ReadReq_mshr_misses::cpu.data 289403 # number of ReadReq MSHR misses
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system.l2c.ReadReq_mshr_misses::total 304138 # number of ReadReq MSHR misses
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system.l2c.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses
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system.l2c.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses
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system.l2c.ReadExReq_mshr_misses::cpu.data 118294 # number of ReadExReq MSHR misses
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system.l2c.ReadExReq_mshr_misses::total 118294 # number of ReadExReq MSHR misses
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system.l2c.demand_mshr_misses::cpu.inst 14735 # number of demand (read+write) MSHR misses
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system.l2c.demand_mshr_misses::cpu.data 407697 # number of demand (read+write) MSHR misses
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system.l2c.demand_mshr_misses::total 422432 # number of demand (read+write) MSHR misses
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system.l2c.overall_mshr_misses::cpu.inst 14735 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::cpu.data 407697 # number of overall MSHR misses
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system.l2c.overall_mshr_misses::total 422432 # number of overall MSHR misses
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system.l2c.ReadReq_mshr_miss_latency::cpu.inst 589436000 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_miss_latency::cpu.data 11581109000 # number of ReadReq MSHR miss cycles
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system.l2c.ReadReq_mshr_miss_latency::total 12170545000 # number of ReadReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 320000 # number of UpgradeReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency::total 320000 # number of UpgradeReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4732225000 # number of ReadExReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::total 4732225000 # number of ReadExReq MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::cpu.inst 589436000 # number of demand (read+write) MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::cpu.data 16313334000 # number of demand (read+write) MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::total 16902770000 # number of demand (read+write) MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu.inst 589436000 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu.data 16313334000 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::total 16902770000 # number of overall MSHR miss cycles
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system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772673000 # number of ReadReq MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_uncacheable_latency::total 772673000 # number of ReadReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1083819500 # number of WriteReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::total 1083819500 # number of WriteReq MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 # number of overall MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses
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system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses
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system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency
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system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency
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system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
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system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.iocache.replacements 41685 # number of replacements
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system.iocache.tagsinuse 1.340325 # Cycle average of tags in use
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system.iocache.total_refs 0 # Total number of references to valid blocks.
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system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
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system.iocache.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit.
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system.iocache.occ_blocks::tsunami.ide 1.340325 # Average occupied blocks per requestor
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system.iocache.occ_percent::tsunami.ide 0.083770 # Average percentage of cache occupancy
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system.iocache.occ_percent::total 0.083770 # Average percentage of cache occupancy
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system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
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system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
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system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
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system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
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system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
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system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
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system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
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system.iocache.overall_misses::total 41725 # number of overall misses
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system.iocache.ReadReq_miss_latency::tsunami.ide 19940998 # number of ReadReq miss cycles
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system.iocache.ReadReq_miss_latency::total 19940998 # number of ReadReq miss cycles
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system.iocache.WriteReq_miss_latency::tsunami.ide 5722300806 # number of WriteReq miss cycles
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system.iocache.WriteReq_miss_latency::total 5722300806 # number of WriteReq miss cycles
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system.iocache.demand_miss_latency::tsunami.ide 5742241804 # number of demand (read+write) miss cycles
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system.iocache.demand_miss_latency::total 5742241804 # number of demand (read+write) miss cycles
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system.iocache.overall_miss_latency::tsunami.ide 5742241804 # number of overall miss cycles
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system.iocache.overall_miss_latency::total 5742241804 # number of overall miss cycles
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system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
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system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
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system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
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system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
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system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
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system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
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system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
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system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
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system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
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system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
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system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
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system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
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system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency
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system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency
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system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
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system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
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system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked
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system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.iocache.fast_writes 0 # number of fast writes performed
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system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.writebacks::writebacks 41512 # number of writebacks
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system.iocache.writebacks::total 41512 # number of writebacks
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system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
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system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
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system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
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system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
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system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
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system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
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system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
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system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
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system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10944998 # number of ReadReq MSHR miss cycles
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system.iocache.ReadReq_mshr_miss_latency::total 10944998 # number of ReadReq MSHR miss cycles
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system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561447990 # number of WriteReq MSHR miss cycles
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system.iocache.WriteReq_mshr_miss_latency::total 3561447990 # number of WriteReq MSHR miss cycles
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system.iocache.demand_mshr_miss_latency::tsunami.ide 3572392988 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 3572392988 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 9057511 # DTB read hits
|
|
system.cpu.dtb.read_misses 10312 # DTB read misses
|
|
system.cpu.dtb.read_acv 210 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 728817 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6352446 # DTB write hits
|
|
system.cpu.dtb.write_misses 1140 # DTB write misses
|
|
system.cpu.dtb.write_acv 157 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 291929 # DTB write accesses
|
|
system.cpu.dtb.data_hits 15409957 # DTB hits
|
|
system.cpu.dtb.data_misses 11452 # DTB misses
|
|
system.cpu.dtb.data_acv 367 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1020746 # DTB accesses
|
|
system.cpu.itb.fetch_hits 4973520 # ITB hits
|
|
system.cpu.itb.fetch_misses 4997 # ITB misses
|
|
system.cpu.itb.fetch_acv 184 # ITB acv
|
|
system.cpu.itb.fetch_accesses 4978517 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 3831097734 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 56137087 # Number of instructions committed
|
|
system.cpu.committedOps 56137087 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses
|
|
system.cpu.num_func_calls 1482242 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 52011214 # number of integer instructions
|
|
system.cpu.num_fp_insts 324192 # number of float instructions
|
|
system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written
|
|
system.cpu.num_mem_refs 15462519 # number of memory refs
|
|
system.cpu.num_load_insts 9094324 # Number of load instructions
|
|
system.cpu.num_store_insts 6368195 # Number of store instructions
|
|
system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.936531 # Percentage of idle cycles
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 192868 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1906
|
|
system.cpu.kern.mode_good::user 1738
|
|
system.cpu.kern.mode_good::idle 168
|
|
system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 1.403193 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4174 # number of times the context was actually changed
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.cpu.icache.replacements 927683 # number of replacements
|
|
system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 508.721464 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.993597 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.993597 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 55220553 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 55220553 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 55220553 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 55220553 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 928354 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 928354 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 928354 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 928354 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13616370500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 13616370500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 13616370500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 13616370500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 13616370500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 13616370500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 56148907 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 56148907 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 85 # number of writebacks
|
|
system.cpu.icache.writebacks::total 85 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 928354 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 928354 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 928354 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10830625500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 10830625500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10830625500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 10830625500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1390115 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 14038335 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.984023 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999969 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999969 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7807536 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 5848554 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 5848554 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 199203 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 199203 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 13656090 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 13656090 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 13656090 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 13656090 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1069110 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1069110 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17201 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 17201 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1373445 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1373445 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1373445 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1373445 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 27121920500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 27121920500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9228484000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 9228484000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245980000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 245980000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 36350404500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 36350404500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 36350404500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 36350404500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 8876646 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 8876646 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6152889 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6152889 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200226 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 200226 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199203 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 199203 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15029535 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15029535 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15029535 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120441 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049462 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085908 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 826586 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 826586 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069110 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1069110 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17201 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17201 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1373445 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1373445 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1373445 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1373445 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23914545000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23914545000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8315479000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8315479000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194377000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194377000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32230024000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 32230024000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32230024000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 32230024000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199607500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|