b38f67d5b7
requestTime -> time
responseTime -> packet.time
Make CPU and memory able to connect to the bus
dev/io_device.cc:
update for request and packet both having a time
hand platform off to port for eventual selection of request modes
dev/io_device.hh:
update for request and packet both havig a time
hand platform off to port for eventual selection of request modes
mem/bus.hh:
Add a device map struct that maps a range to a portId
- Which needs work it theory it should be an interval tree
- but it is a list and works fine right now
Add a function called findPort which returns port for an addr range
Add a deviceBlockSize function that really shouldn't exist, but it
was easier than fixing the translating port
mem/packet.hh:
add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
remove requestTime/responseTime for just time in request which
is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
Fix for new bus object
--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
127 lines
3.7 KiB
C++
127 lines
3.7 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file Definition of a bus object.
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*/
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#include "bus.hh"
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#include "sim/builder.hh"
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/** Function called by the port when the bus is recieving a Timing
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* transaction.*/
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bool
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Bus::recvTiming(Packet &pkt, int id)
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{
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panic("I need to be implemented, but not right now.");
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}
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Port *
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Bus::findPort(Addr addr, int id)
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{
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/* An interval tree would be a better way to do this. --ali. */
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int dest_id = -1;
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int i = 0;
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bool found = false;
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while (i < portList.size() && !found)
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{
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if (portList[i].range == addr) {
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dest_id = portList[i].portId;
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found = true;
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}
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}
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assert(dest_id != -1 && "Unable to find destination");
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// we shouldn't be sending this back to where it came from
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assert(dest_id != id);
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return interfaces[dest_id];
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}
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/** Function called by the port when the bus is recieving a Atomic
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* transaction.*/
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Tick
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Bus::recvAtomic(Packet &pkt, int id)
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{
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return findPort(pkt.addr, id)->sendAtomic(pkt);
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}
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/** Function called by the port when the bus is recieving a Functional
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* transaction.*/
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void
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Bus::recvFunctional(Packet &pkt, int id)
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{
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findPort(pkt.addr, id)->sendFunctional(pkt);
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}
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/** Function called by the port when the bus is recieving a status change.*/
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void
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Bus::recvStatusChange(Port::Status status, int id)
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{
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assert(status == Port:: RangeChange &&
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"The other statuses need to be implemented.");
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Port *port = interfaces[id];
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AddrRangeList ranges;
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bool owner;
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port->getPeerAddressRanges(ranges, owner);
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// not dealing with snooping yet either
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assert(owner == true);
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// or multiple ranges
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assert(ranges.size() == 1);
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DevMap dm;
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dm.portId = id;
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dm.range = ranges.front();
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portList.push_back(dm);
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}
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void
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Bus::BusPort::addressRanges(AddrRangeList &range_list, bool &owner)
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{
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panic("I'm not implemented.\n");
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
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Param<int> bus_id;
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END_DECLARE_SIM_OBJECT_PARAMS(Bus)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
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INIT_PARAM(bus_id, "junk bus id")
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END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
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CREATE_SIM_OBJECT(Bus)
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{
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return new Bus(getInstanceName());
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}
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REGISTER_SIM_OBJECT("Bus", Bus)
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