gem5/arch/sparc/isa
Gabe Black 818f3ae22f SPARC compiles for SE!
arch/sparc/isa/decoder.isa:
    Replaced register number munging with RdLow and RdHigh operands.
arch/sparc/isa/formats/mem.isa:
    Fixed how the address calculation code is dealt with.
arch/sparc/isa/operands.isa:
    Changed the tabbing so that the whole oeprands block was consistent, and added RdLow and RdHigh operands. These registers are used when Rd is meant to refer to a pair of registers, rather than just one.
arch/sparc/isa_traits.hh:
    Moved some functions to the new (to SPARC) utility.hh file. Also, dummy Fpcr_DepTag and Uniq_DepTag DepTags were added to pacify Tru64. These need to be removed, and Tru64 needs to not be compiled in if it isn't appropriate.
arch/sparc/regfile.hh:
    Changed regSpace to have the correct size.
arch/sparc/utility.hh:
    A new file for sparc to match the one for alpha.

--HG--
extra : convert_revision : ff6b529093d15f327ec11f067ad533bacdba9932
2006-03-28 19:36:34 -05:00
..
formats SPARC compiles for SE! 2006-03-28 19:36:34 -05:00
base.isa Clean up and fix for compilation 2006-03-17 14:02:38 -05:00
bitfields.isa Fixed a couple typos 2006-03-17 14:25:54 -05:00
decoder.isa SPARC compiles for SE! 2006-03-28 19:36:34 -05:00
formats.isa Fixups towards compiling. 2006-03-16 13:58:50 -05:00
includes.isa Fixups towards compiling. 2006-03-16 13:58:50 -05:00
main.isa Minor cleanup of include-handling code in isa_parser.py. 2006-02-09 22:27:41 -05:00
operands.isa SPARC compiles for SE! 2006-03-28 19:36:34 -05:00