Lisa Hsu 551ba56ae2 little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem). ... RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you. src/cpu/memtest/memtest.hh: src/cpu/o3/fetch.hh: src/cpu/o3/lsq.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/simple/atomic.hh: src/cpu/simple/timing.hh: Fix RangeSize arguments src/dev/alpha/tsunami_cchip.cc: src/dev/alpha/tsunami_io.cc: src/dev/alpha/tsunami_pchip.cc: src/dev/baddev.cc: pioSize indicates SIZE, not a mask --HG-- extra : convert_revision : d385521fcfe58f8dffc8622260937e668a47a948		2006-12-15 17:55:47 -05:00
..
atomic.cc	More changes to get SPARC fs closer. Now at 1.2M cycles before difference	2006-12-04 00:54:40 -05:00
atomic.hh	little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).	2006-12-15 17:55:47 -05:00
base.cc	Updates to support new interrupt processing and removal of PcPAL.	2006-11-12 20:15:30 -05:00
base.hh	Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.	2006-12-12 09:58:40 -08:00
timing.cc	Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.	2006-11-29 16:07:55 -05:00
timing.hh	little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).	2006-12-15 17:55:47 -05:00