54d4220b00
Following with the previous check-in, ExecContext now refers only to the interface provided to the ISA in order to access CPU state. ThreadContext refers to the interface provided to all objects outside the CPU in order to access thread state. SimpleThread provides all thread state and the interface to access it, and is suitable for simple execution models such as the SimpleCPU.
src/SConscript:
Include thread state file.
src/arch/alpha/ev5.cc:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/thread_context.hh:
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/cpu.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
Rename CPUExecContext to SimpleThread.
src/cpu/base_dyn_inst.hh:
Make thread member variables protected..
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/cpu.hh:
Make various members of ThreadState protected.
src/cpu/o3/alpha_cpu_impl.hh:
Push generation of TranslatingPort into the CPU itself.
Make various members of ThreadState protected.
src/cpu/o3/thread_state.hh:
Pull a lot of common code into the base ThreadState class.
src/cpu/ozone/thread_state.hh:
Rename CPUExecContext to SimpleThread, move a lot of common code into base ThreadState class.
src/cpu/thread_state.hh:
Push a lot of common code into base ThreadState class. This goes along with renaming CPUExecContext to SimpleThread, and making it derive from ThreadState.
src/cpu/simple_thread.cc:
Rename CPUExecContext to SimpleThread, make it derive from ThreadState. This helps push a lot of common code/state into a single class that can be used by all CPUs.
src/cpu/simple_thread.hh:
Rename CPUExecContext to SimpleThread, make it derive from ThreadState.
src/kern/system_events.cc:
Rename cpu_exec_context to thread_context.
src/sim/process.hh:
Remove unused forward declaration.
--HG--
rename : src/cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : src/cpu/cpu_exec_context.hh => src/cpu/simple_thread.hh
extra : convert_revision : 2ed617aa80b64016cb9270f75352607cca032733
475 lines
12 KiB
C++
475 lines
12 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#include "arch/utility.hh"
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#include "base/cprintf.hh"
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/pollevent.hh"
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#include "base/range.hh"
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#include "base/stats/events.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/profile.hh"
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#include "cpu/sampler/sampler.hh"
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#include "cpu/simple/base.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/smt.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "kern/kernel_stats.hh"
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#include "mem/packet_impl.hh"
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#include "sim/builder.hh"
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#include "sim/byteswap.hh"
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#include "sim/debug.hh"
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#include "sim/host.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#if FULL_SYSTEM
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#include "base/remote_gdb.hh"
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#include "sim/system.hh"
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#include "arch/tlb.hh"
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#include "arch/stacktrace.hh"
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#include "arch/vtophys.hh"
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#else // !FULL_SYSTEM
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#include "mem/mem_object.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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using namespace TheISA;
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BaseSimpleCPU::BaseSimpleCPU(Params *p)
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: BaseCPU(p), mem(p->mem), thread(NULL)
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{
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#if FULL_SYSTEM
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thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
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#else
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thread = new SimpleThread(this, /* thread_num */ 0, p->process,
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/* asid */ 0, mem);
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#endif // !FULL_SYSTEM
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thread->setStatus(ThreadContext::Suspended);
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tc = thread->getTC();
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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lastIcacheStall = 0;
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lastDcacheStall = 0;
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threadContexts.push_back(tc);
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}
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BaseSimpleCPU::~BaseSimpleCPU()
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{
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}
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void
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BaseSimpleCPU::deallocateContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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BaseSimpleCPU::haltContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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BaseSimpleCPU::regStats()
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{
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using namespace Stats;
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BaseCPU::regStats();
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numInsts
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.name(name() + ".num_insts")
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.desc("Number of instructions executed")
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;
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numMemRefs
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.name(name() + ".num_refs")
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.desc("Number of memory references")
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;
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notIdleFraction
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.name(name() + ".not_idle_fraction")
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.desc("Percentage of non-idle cycles")
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;
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idleFraction
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.name(name() + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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icacheStallCycles
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.name(name() + ".icache_stall_cycles")
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.desc("ICache total stall cycles")
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.prereq(icacheStallCycles)
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;
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dcacheStallCycles
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.name(name() + ".dcache_stall_cycles")
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.desc("DCache total stall cycles")
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.prereq(dcacheStallCycles)
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;
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icacheRetryCycles
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.name(name() + ".icache_retry_cycles")
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.desc("ICache total retry cycles")
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.prereq(icacheRetryCycles)
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;
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dcacheRetryCycles
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.name(name() + ".dcache_retry_cycles")
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.desc("DCache total retry cycles")
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.prereq(dcacheRetryCycles)
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;
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idleFraction = constant(1.0) - notIdleFraction;
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}
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void
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BaseSimpleCPU::resetStats()
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{
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startNumInst = numInst;
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// notIdleFraction = (_status != Idle);
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}
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void
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BaseSimpleCPU::serialize(ostream &os)
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{
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BaseCPU::serialize(os);
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SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc", name()));
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thread->serialize(os);
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}
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void
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BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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BaseCPU::unserialize(cp, section);
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UNSERIALIZE_SCALAR(inst);
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thread->unserialize(cp, csprintf("%s.xc", section));
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}
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void
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change_thread_state(int thread_number, int activate, int priority)
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{
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}
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Fault
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BaseSimpleCPU::copySrcTranslate(Addr src)
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{
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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int offset = src & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(src & PageMask) != ((src + blk_size) & PageMask) &&
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(src >> 40) != 0xfffffc) {
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warn("Copied block source spans pages %x.", src);
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no_warn = false;
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}
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memReq->reset(src & ~(blk_size - 1), blk_size);
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// translate to physical address
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Fault fault = thread->translateDataReadReq(req);
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if (fault == NoFault) {
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thread->copySrcAddr = src;
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thread->copySrcPhysAddr = memReq->paddr + offset;
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} else {
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assert(!fault->isAlignmentFault());
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thread->copySrcAddr = 0;
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thread->copySrcPhysAddr = 0;
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}
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return fault;
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#else
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return NoFault;
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#endif
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}
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Fault
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BaseSimpleCPU::copy(Addr dest)
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{
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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uint8_t data[blk_size];
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//assert(thread->copySrcAddr);
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int offset = dest & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(dest & PageMask) != ((dest + blk_size) & PageMask) &&
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(dest >> 40) != 0xfffffc) {
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no_warn = false;
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warn("Copied block destination spans pages %x. ", dest);
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}
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memReq->reset(dest & ~(blk_size -1), blk_size);
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// translate to physical address
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Fault fault = thread->translateDataWriteReq(req);
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if (fault == NoFault) {
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Addr dest_addr = memReq->paddr + offset;
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// Need to read straight from memory since we have more than 8 bytes.
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memReq->paddr = thread->copySrcPhysAddr;
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thread->mem->read(memReq, data);
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memReq->paddr = dest_addr;
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thread->mem->write(memReq, data);
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if (dcacheInterface) {
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memReq->cmd = Copy;
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memReq->completionEvent = NULL;
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memReq->paddr = thread->copySrcPhysAddr;
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memReq->dest = dest_addr;
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memReq->size = 64;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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dcacheInterface->access(memReq);
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}
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}
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else
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assert(!fault->isAlignmentFault());
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return fault;
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#else
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panic("copy not implemented");
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return NoFault;
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#endif
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}
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#if FULL_SYSTEM
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Addr
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BaseSimpleCPU::dbg_vtophys(Addr addr)
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{
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return vtophys(tc, addr);
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}
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#endif // FULL_SYSTEM
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#if FULL_SYSTEM
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void
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BaseSimpleCPU::post_interrupt(int int_num, int index)
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{
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BaseCPU::post_interrupt(int_num, index);
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if (thread->status() == ThreadContext::Suspended) {
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DPRINTF(IPI,"Suspended Processor awoke\n");
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thread->activate();
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}
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}
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#endif // FULL_SYSTEM
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void
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BaseSimpleCPU::checkForInterrupts()
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{
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#if FULL_SYSTEM
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if (checkInterrupts && check_interrupts() && !thread->inPalMode()) {
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int ipl = 0;
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int summary = 0;
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checkInterrupts = false;
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if (thread->readMiscReg(IPR_SIRR)) {
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for (int i = INTLEVEL_SOFTWARE_MIN;
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i < INTLEVEL_SOFTWARE_MAX; i++) {
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if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
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// See table 4-19 of 21164 hardware reference
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ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
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summary |= (ULL(1) << i);
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}
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}
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}
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uint64_t interrupts = thread->cpu->intr_status();
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for (int i = INTLEVEL_EXTERNAL_MIN;
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i < INTLEVEL_EXTERNAL_MAX; i++) {
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if (interrupts & (ULL(1) << i)) {
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// See table 4-19 of 21164 hardware reference
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ipl = i;
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summary |= (ULL(1) << i);
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}
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}
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if (thread->readMiscReg(IPR_ASTRR))
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panic("asynchronous traps not implemented\n");
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if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
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thread->setMiscReg(IPR_ISR, summary);
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thread->setMiscReg(IPR_INTID, ipl);
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Fault(new InterruptFault)->invoke(tc);
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DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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thread->readMiscReg(IPR_IPLR), ipl, summary);
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}
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}
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#endif
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}
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Fault
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BaseSimpleCPU::setupFetchRequest(Request *req)
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{
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// set up memory request for instruction fetch
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DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
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thread->readNextPC(),thread->readNextNPC());
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req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
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(FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0,
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thread->readPC());
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Fault fault = thread->translateInstReq(req);
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return fault;
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}
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void
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BaseSimpleCPU::preExecute()
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{
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// maintain $r0 semantics
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thread->setIntReg(ZeroReg, 0);
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#if THE_ISA == ALPHA_ISA
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thread->setFloatReg(ZeroReg, 0.0);
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#endif // ALPHA_ISA
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// keep an instruction count
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numInst++;
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numInsts++;
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thread->funcExeInst++;
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// check for instruction-count-based events
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comInstEventQueue[0]->serviceEvents(numInst);
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// decode the instruction
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inst = gtoh(inst);
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curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC()));
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traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst,
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thread->readPC());
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DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
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curStaticInst->getName(), curStaticInst->getOpcode(),
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curStaticInst->machInst);
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#if FULL_SYSTEM
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thread->setInst(inst);
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#endif // FULL_SYSTEM
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}
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void
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BaseSimpleCPU::postExecute()
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{
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#if FULL_SYSTEM
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if (system->kernelBinning->fnbin) {
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assert(thread->getKernelStats());
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system->kernelBinning->execute(tc, inst);
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}
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if (thread->profile) {
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bool usermode =
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(thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
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thread->profilePC = usermode ? 1 : thread->readPC();
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ProfileNode *node = thread->profile->consume(tc, inst);
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if (node)
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thread->profileNode = node;
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}
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#endif
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if (curStaticInst->isMemRef()) {
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numMemRefs++;
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}
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if (curStaticInst->isLoad()) {
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++numLoad;
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comLoadEventQueue[0]->serviceEvents(numLoad);
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}
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traceFunctions(thread->readPC());
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if (traceData) {
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traceData->finalize();
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}
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}
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void
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BaseSimpleCPU::advancePC(Fault fault)
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{
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if (fault != NoFault) {
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#if FULL_SYSTEM
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fault->invoke(tc);
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#else // !FULL_SYSTEM
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fatal("fault (%s) detected @ PC %08p", fault->name(), thread->readPC());
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#endif // FULL_SYSTEM
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}
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else {
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// go to the next instruction
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thread->setPC(thread->readNextPC());
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#if THE_ISA == ALPHA_ISA
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thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
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#else
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thread->setNextPC(thread->readNextNPC());
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thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
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#endif
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}
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#if FULL_SYSTEM
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Addr oldpc;
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do {
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oldpc = thread->readPC();
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system->pcEventQueue.service(tc);
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} while (oldpc != thread->readPC());
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#endif
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}
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