54b47bc5ae
arch/mips/faults.hh:
remove nonsense
arch/mips/isa/base.isa:
define R31
arch/mips/isa/bitfields.isa:
forgotten bitfields
arch/mips/isa/decoder.isa:
INT64 -> int64_t
arch/mips/isa/formats.isa:
fix comments
arch/mips/isa/formats/branch.isa:
Branch -> BranchLikely
RB -> RT
arch/mips/isa/formats/fp.isa:
Make FP ops generates
arch/mips/isa/formats/mem.isa:
RA,RB -> RS,RT
arch/mips/isa/formats/noop.isa:
Rc -> Rd
arch/mips/isa/formats/util.isa:
forgot brace and semicolon
arch/mips/isa/includes.isa:
remove unnecessary files
arch/mips/isa_traits.hh:
spacing
cpu/static_inst.hh:
add cond_delay_slot flag
--HG--
extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
90 lines
3.1 KiB
C++
90 lines
3.1 KiB
C++
// -*- mode:c++ -*-
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////////////////////////////////////////////////////////////////////
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//
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// Floating Point operate instructions
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//
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output header {{
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/**
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* Base class for FP operations.
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*/
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class FPOp : public MipsStaticInst
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{
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protected:
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/// Constructor
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FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return "Disassembly of integer instruction\n";
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}
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}};
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def template FloatingPointExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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//These are set to constants when the execute method
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//is generated
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bool useCc = ;
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bool checkPriv = ;
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//Attempt to execute the instruction
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try
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{
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checkPriv;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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}
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//If we have an exception for some reason,
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//deal with it
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catch(MipsException except)
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{
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//Deal with exception
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return No_Fault;
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}
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//Write the resulting state to the execution context
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%(op_wb)s;
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if(useCc)
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{
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xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
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xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
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xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
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xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
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xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
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xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
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xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
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xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
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}
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return No_Fault;
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}
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}};
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// Primary format for integer operate instructions:
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def format FloatOp(code, *flags) {{
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iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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// Primary format for integer operate instructions:
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def format Float64Op(code, *flags) {{
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iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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