53e777d683
Context IDs used to be declared as ad hoc (usually as int). This changeset introduces a typedef for ContextIDs and a constant for invalid context IDs.
198 lines
6.7 KiB
C++
198 lines
6.7 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "cpu/base.hh"
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#include "cpu/quiesce_event.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Context.hh"
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#include "sim/full_system.hh"
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void
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ThreadContext::compare(ThreadContext *one, ThreadContext *two)
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{
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DPRINTF(Context, "Comparing thread contexts\n");
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// First loop through the integer registers.
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for (int i = 0; i < TheISA::NumIntRegs; ++i) {
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TheISA::IntReg t1 = one->readIntReg(i);
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TheISA::IntReg t2 = two->readIntReg(i);
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if (t1 != t2)
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panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
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i, t1, t2);
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
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TheISA::FloatRegBits t1 = one->readFloatRegBits(i);
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TheISA::FloatRegBits t2 = two->readFloatRegBits(i);
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if (t1 != t2)
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panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
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i, t1, t2);
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}
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for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
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TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
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TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
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if (t1 != t2)
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panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
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i, t1, t2);
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}
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// loop through the Condition Code registers.
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for (int i = 0; i < TheISA::NumCCRegs; ++i) {
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TheISA::CCReg t1 = one->readCCReg(i);
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TheISA::CCReg t2 = two->readCCReg(i);
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if (t1 != t2)
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panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
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i, t1, t2);
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}
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if (!(one->pcState() == two->pcState()))
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panic("PC state doesn't match.");
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int id1 = one->cpuId();
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int id2 = two->cpuId();
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if (id1 != id2)
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panic("CPU ids don't match, one: %d, two: %d", id1, id2);
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const ContextID cid1 = one->contextId();
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const ContextID cid2 = two->contextId();
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if (cid1 != cid2)
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panic("Context ids don't match, one: %d, two: %d", id1, id2);
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}
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void
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serialize(ThreadContext &tc, CheckpointOut &cp)
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{
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using namespace TheISA;
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FloatRegBits floatRegs[NumFloatRegs];
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for (int i = 0; i < NumFloatRegs; ++i)
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floatRegs[i] = tc.readFloatRegBitsFlat(i);
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// This is a bit ugly, but needed to maintain backwards
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// compatibility.
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arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
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IntReg intRegs[NumIntRegs];
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for (int i = 0; i < NumIntRegs; ++i)
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intRegs[i] = tc.readIntRegFlat(i);
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SERIALIZE_ARRAY(intRegs, NumIntRegs);
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#ifdef ISA_HAS_CC_REGS
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CCReg ccRegs[NumCCRegs];
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for (int i = 0; i < NumCCRegs; ++i)
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ccRegs[i] = tc.readCCRegFlat(i);
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SERIALIZE_ARRAY(ccRegs, NumCCRegs);
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#endif
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tc.pcState().serialize(cp);
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// thread_num and cpu_id are deterministic from the config
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}
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void
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unserialize(ThreadContext &tc, CheckpointIn &cp)
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{
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using namespace TheISA;
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FloatRegBits floatRegs[NumFloatRegs];
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// This is a bit ugly, but needed to maintain backwards
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// compatibility.
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arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
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for (int i = 0; i < NumFloatRegs; ++i)
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tc.setFloatRegBitsFlat(i, floatRegs[i]);
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IntReg intRegs[NumIntRegs];
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UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
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for (int i = 0; i < NumIntRegs; ++i)
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tc.setIntRegFlat(i, intRegs[i]);
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#ifdef ISA_HAS_CC_REGS
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CCReg ccRegs[NumCCRegs];
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UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
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for (int i = 0; i < NumCCRegs; ++i)
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tc.setCCRegFlat(i, ccRegs[i]);
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#endif
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PCState pcState;
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pcState.unserialize(cp);
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tc.pcState(pcState);
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// thread_num and cpu_id are deterministic from the config
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}
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void
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takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
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{
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assert(ntc.getProcessPtr() == otc.getProcessPtr());
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ntc.setStatus(otc.status());
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ntc.copyArchRegs(&otc);
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ntc.setContextId(otc.contextId());
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ntc.setThreadId(otc.threadId());
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if (FullSystem) {
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assert(ntc.getSystemPtr() == otc.getSystemPtr());
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BaseCPU *ncpu(ntc.getCpuPtr());
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assert(ncpu);
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EndQuiesceEvent *oqe(otc.getQuiesceEvent());
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assert(oqe);
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assert(oqe->tc == &otc);
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BaseCPU *ocpu(otc.getCpuPtr());
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assert(ocpu);
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EndQuiesceEvent *nqe(ntc.getQuiesceEvent());
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assert(nqe);
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assert(nqe->tc == &ntc);
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if (oqe->scheduled()) {
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ncpu->schedule(nqe, oqe->when());
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ocpu->deschedule(oqe);
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}
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}
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otc.setStatus(ThreadContext::Halted);
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}
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