gem5/python/m5/objects
Ali Saidi 53d93ef918 add a bridge object, modify bus object to be able to connect to other buses or bridges without panicing
SConscript:
    add new cc files to scons
mem/bus.cc:
mem/bus.hh:
    implement addressRanges() on the bus.
    propigate address ranges to anyone who is interested stripping out ranges of who your propigating to (to avoid livelock)
mem/packet.hh:
    add intersect function that returns true if two packets touch at least one byte of the same data (for functional access)
    add fixPacket() that will eventually take the correct action giving a timing and functional packet, right now it panics
mem/physical.cc:
    Don't panic if the physical memory recieves a status change, just ignore.

--HG--
extra : convert_revision : d470d51f2fb1db2700ad271e09792315ef33ba01
2006-04-28 15:37:48 -04:00
..
AlphaConsole.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
AlphaFullCPU.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
AlphaTLB.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
BadDevice.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
BaseCache.py Standardize clock parameter names to 'clock'. 2005-06-01 21:44:00 -04:00
BaseCPU.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
Bridge.py add a bridge object, modify bus object to be able to connect to other buses or bridges without panicing 2006-04-28 15:37:48 -04:00
Bus.py Implement a very very simple bus 2006-03-25 18:31:20 -05:00
CoherenceProtocol.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Device.py make ide disk work for newmem 2006-04-20 17:14:30 -04:00
DiskImage.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Ethernet.py Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working 2006-04-24 19:31:50 -04:00
Ide.py make ide disk work for newmem 2006-04-20 17:14:30 -04:00
IntrControl.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
MemObject.py Update functional memory to have a response event 2006-02-23 13:51:54 -05:00
MemTest.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Pci.py make ide disk work for newmem 2006-04-20 17:14:30 -04:00
PhysicalMemory.py make ide disk work for newmem 2006-04-20 17:14:30 -04:00
Platform.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Process.py add translations for new sections that are mmapped or when the brk 2006-03-15 17:04:50 -05:00
Repl.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
Root.py More progress toward actually running a program. 2006-03-01 18:45:50 -05:00
SimConsole.py Major cleanup of python config code. 2005-05-29 01:14:50 -04:00
SimpleDisk.py fixes for newmem 2006-04-06 14:57:51 -04:00
System.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
Tsunami.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00
Uart.py fullsys now builds and runs for about one cycle 2006-04-11 13:42:47 -04:00