cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
855 lines
97 KiB
Text
855 lines
97 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.164572 # Number of seconds simulated
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sim_ticks 164572262000 # Number of ticks simulated
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final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 185108 # Simulator instruction rate (inst/s)
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host_op_rate 195599 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 53440170 # Simulator tick rate (ticks/s)
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host_mem_usage 241944 # Number of bytes of host memory used
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host_seconds 3079.56 # Real time elapsed on the host
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sim_insts 570051585 # Number of instructions simulated
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sim_ops 602359791 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1701952 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1749376 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 47424 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 47424 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 162432 # Number of bytes written to this memory
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system.physmem.bytes_written::total 162432 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 741 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 26593 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 27334 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 2538 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 2538 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 288165 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 10341670 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 10629835 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 288165 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 288165 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 986995 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 986995 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 986995 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 288165 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 10341670 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 11616830 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 27336 # Total number of read requests seen
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system.physmem.writeReqs 2538 # Total number of write requests seen
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system.physmem.cpureqs 29874 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 1749376 # Total number of bytes read from memory
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system.physmem.bytesWritten 162432 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 1749376 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 162432 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 1695 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 1726 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 1726 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 1753 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 1671 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 1695 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 1674 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 1668 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 1735 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 1761 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 1742 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 1724 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 1686 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 161 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 158 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 158 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 156 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 158 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 156 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 160 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 164 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 162 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 160 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 164572246000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 27336 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 2538 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 40 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 921339250 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 1672034250 # Sum of mem lat for all requests
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system.physmem.totBusLat 136675000 # Total cycles spent in databus access
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system.physmem.totBankLat 614020000 # Total cycles spent in bank access
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system.physmem.avgQLat 33704.25 # Average queueing delay per request
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system.physmem.avgBankLat 22461.95 # Average bank access latency per request
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system.physmem.avgBusLat 4999.82 # Average bus latency per request
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system.physmem.avgMemAccLat 61166.02 # Average memory access latency
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system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.09 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.01 # Average read queue length over time
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system.physmem.avgWrQLen 7.98 # Average write queue length over time
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system.physmem.readRowHits 16887 # Number of row buffer hits during reads
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system.physmem.writeRowHits 1046 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 61.78 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes
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system.physmem.avgGap 5508878.82 # Average gap between requests
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system.cpu.branchPred.lookups 85156760 # Number of BP lookups
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system.cpu.branchPred.condPredicted 79937555 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 2342179 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 47221599 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 46882126 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 99.281107 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1427254 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 1090 # Number of incorrect RAS predictions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 48 # Number of system calls
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system.cpu.numCycles 329144525 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 68500133 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 666893560 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 85156760 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 48309380 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 129633878 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 13101459 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 119325440 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 311 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 67084243 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 755399 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 328191292 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.165364 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.193928 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 198557643 60.50% 60.50% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 20911639 6.37% 66.87% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 4968720 1.51% 68.39% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 14346044 4.37% 72.76% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 8890886 2.71% 75.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 9446619 2.88% 78.35% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 4399795 1.34% 79.69% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 5788532 1.76% 81.45% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 60881414 18.55% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 328191292 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.258721 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.026142 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 92969239 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 96174869 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 107931491 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 20385682 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 10730011 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 4738020 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 1580 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 703286632 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 5586 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 10730011 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 107159029 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 14373843 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 39888 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 114052351 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 81836170 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 694854437 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 59359193 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 20344162 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 721334030 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 3230715755 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 3230715627 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 93916657 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1707 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 1652 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 170570480 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 172204690 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 80467392 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 21722432 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 29158581 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 680011931 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2919 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 645607270 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 1367531 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 77472778 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 193408701 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 215 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 328191292 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.967168 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 85141419 25.94% 46.69% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 76162032 23.21% 69.90% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 40819070 12.44% 82.34% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 14914631 4.54% 95.68% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 328191292 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 216791 5.75% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 2693843 71.39% 77.14% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 862775 22.86% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 403382320 62.48% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 165566556 25.65% 88.13% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 76651819 11.87% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 645607270 # Type of FU issued
|
|
system.cpu.iq.rate 1.961470 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 3773409 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.005845 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 1624546736 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 757499752 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 637553210 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 649380659 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 30362769 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 23252097 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 121645 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 12371 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 10246379 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 12896 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 35853 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 10730011 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 795888 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 91006 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 680017934 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 687807 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 172204690 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 80467392 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1591 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 32670 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 15237 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 12371 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 1357657 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 1460843 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 2818500 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 641514820 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 163491606 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 4092450 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 3084 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 239364786 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 74674061 # Number of branches executed
|
|
system.cpu.iew.exec_stores 75873180 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.949037 # Inst execution rate
|
|
system.cpu.iew.wb_sent 638961643 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 637553226 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 418732313 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 650059572 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.937001 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.644145 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 77666777 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 2340669 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 317461281 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.897428 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.237399 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 93255759 29.38% 29.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 104348924 32.87% 62.25% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 42985847 13.54% 75.79% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 8791848 2.77% 78.56% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 25959048 8.18% 86.73% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 12901404 4.06% 90.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 7629324 2.40% 93.20% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 1168492 0.37% 93.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 20420635 6.43% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 317461281 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 570051636 # Number of instructions committed
|
|
system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 219173606 # Number of memory references committed
|
|
system.cpu.commit.loads 148952593 # Number of loads committed
|
|
system.cpu.commit.membars 1328 # Number of memory barriers committed
|
|
system.cpu.commit.branches 70892524 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 533522631 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 997573 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 20420635 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 977066653 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1370815087 # The number of ROB writes
|
|
system.cpu.timesIdled 44013 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 953233 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 570051585 # Number of Instructions Simulated
|
|
system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.577394 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.577394 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.731919 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.731919 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 3204307958 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 663049374 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 234758339 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2656 # number of misc regfile writes
|
|
system.cpu.icache.replacements 66 # number of replacements
|
|
system.cpu.icache.tagsinuse 690.513263 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 67083102 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 830 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 80823.014458 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 690.513263 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.337165 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.337165 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 67083102 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 67083102 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 67083102 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 67083102 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 67083102 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 67083102 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1141 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 54478999 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 54478999 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 54478999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 54478999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 54478999 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 54478999 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 67084243 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 67084243 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 67084243 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 67084243 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 67084243 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 67084243 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47746.712533 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 47746.712533 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 47746.712533 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 47746.712533 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 41.142857 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 832 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 832 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 832 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 832 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 832 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 832 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42177999 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 42177999 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42177999 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 42177999 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42177999 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 42177999 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50694.710337 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50694.710337 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50694.710337 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 50694.710337 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50694.710337 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 50694.710337 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 2560 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 22366.880466 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 517335 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 24173 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 21.401357 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 20764.354614 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 652.476885 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 950.048967 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.633678 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.019912 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.028993 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.682583 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 88 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 192787 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 192875 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 421643 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 421643 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 225378 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 225378 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 88 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 418165 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 418253 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 88 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 418165 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 418253 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 743 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 4811 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 5554 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 21791 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 21791 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 743 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 26602 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 27345 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 743 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 26602 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 27345 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40442500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 687347500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 727790000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1581776500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1581776500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 40442500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 2269124000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 2309566500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 40442500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 2269124000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 2309566500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 831 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 197598 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 198429 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 421643 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 421643 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247169 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 247169 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 831 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 444767 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 445598 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 831 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 444767 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 445598 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.894103 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024347 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.027990 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088162 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.088162 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.894103 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.059811 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.061367 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.894103 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.059811 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.061367 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54431.359354 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 142869.985450 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 131038.890889 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72588.522785 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72588.522785 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54431.359354 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85299.000075 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 84460.285244 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54431.359354 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85299.000075 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 84460.285244 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 2538 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 2538 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 741 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4804 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 5545 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21791 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21791 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 741 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 26595 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 27336 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 741 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 26595 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 27336 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31149092 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 627893373 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 659042465 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310013362 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310013362 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149092 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937906735 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1969055827 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149092 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937906735 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1969055827 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027945 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088162 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088162 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.061347 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061347 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42036.561404 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130702.200874 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118853.465284 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.175072 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.175072 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42036.561404 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72867.333521 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72031.600344 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42036.561404 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72867.333521 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72031.600344 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 440669 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 197567614 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 444765 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 444.206747 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 314058000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4091.484070 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.998897 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.998897 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 131523721 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 131523721 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 66041240 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 66041240 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1324 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1324 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 197564961 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 197564961 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 197564961 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 197564961 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 341919 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 341919 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 3376291 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 3376291 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3718210 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3718210 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3718210 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3718210 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073533500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5073533500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 40705228766 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 40705228766 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 337500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 337500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 45778762266 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 45778762266 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 45778762266 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 45778762266 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 131865640 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 131865640 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1346 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1346 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 201283171 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 201283171 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 201283171 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 201283171 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002593 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.002593 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048637 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.048637 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016345 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016345 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.018473 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.018473 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.018473 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.018473 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.407635 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.407635 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12056.196805 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 12056.196805 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15340.909091 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 12312.043232 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 12312.043232 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 148065 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 30 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.930261 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 421643 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 421643 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144320 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 144320 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3129122 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3129122 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3273442 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3273442 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3273442 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3273442 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197599 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 197599 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247169 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 247169 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 444768 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 444768 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 444768 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836404500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836404500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932827321 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6932827321 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932827321 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6932827321 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.346429 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.346429 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|