210 lines
7.7 KiB
C++
210 lines
7.7 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "base/bitfield.hh"
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#include "dev/x86/i8259.hh"
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Tick
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X86ISA::I8259::read(PacketPtr pkt)
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{
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assert(pkt->getSize() == 1);
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switch(pkt->getAddr() - pioAddr)
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{
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case 0x0:
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if (readIRR) {
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DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
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pkt->set(IRR);
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} else {
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DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
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pkt->set(ISR);
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}
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break;
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case 0x1:
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DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
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pkt->set(IMR);
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break;
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}
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return latency;
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}
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Tick
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X86ISA::I8259::write(PacketPtr pkt)
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{
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assert(pkt->getSize() == 1);
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uint8_t val = pkt->get<uint8_t>();
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switch (pkt->getAddr() - pioAddr) {
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case 0x0:
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if (bits(val, 4)) {
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DPRINTF(I8259, "Received initialization command word 1.\n");
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IMR = 0;
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edgeTriggered = bits(val, 3);
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DPRINTF(I8259, "%s triggered mode.\n",
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edgeTriggered ? "Edge" : "Level");
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cascadeMode = !bits(val, 1);
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DPRINTF(I8259, "%s mode.\n",
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cascadeMode ? "Cascade" : "Single");
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expectICW4 = bits(val, 0);
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initControlWord = 1;
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DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
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} else if (bits(val, 4, 3) == 0) {
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DPRINTF(I8259, "Received operation command word 2.\n");
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switch (bits(val, 7, 5)) {
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case 0x0:
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DPRINTF(I8259,
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"Subcommand: Rotate in auto-EOI mode (clear).\n");
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break;
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case 0x1:
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DPRINTF(I8259, "Subcommand: Nonspecific EOI.\n");
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break;
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case 0x2:
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DPRINTF(I8259, "Subcommand: No operation.\n");
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break;
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case 0x3:
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DPRINTF(I8259, "Subcommand: Specific EIO.");
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DPRINTF(I8259, "Reset In-Service bit %d.\n", bits(val, 2, 0));
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break;
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case 0x4:
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DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
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break;
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case 0x5:
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DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
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break;
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case 0x6:
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DPRINTF(I8259, "Subcommand: Set priority command.\n");
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DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
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bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
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break;
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case 0x7:
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DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
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DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
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bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
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break;
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}
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} else if (bits(val, 4, 3) == 1) {
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DPRINTF(I8259, "Received operation command word 3.\n");
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if (bits(val, 7)) {
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DPRINTF(I8259, "%s special mask mode.\n",
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bits(val, 6) ? "Set" : "Clear");
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}
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if (bits(val, 1)) {
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readIRR = bits(val, 0);
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DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
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}
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}
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break;
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case 0x1:
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switch (initControlWord) {
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case 0x0:
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DPRINTF(I8259, "Received operation command word 1.\n");
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DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
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IMR = val;
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break;
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case 0x1:
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DPRINTF(I8259, "Received initialization command word 2.\n");
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DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
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val & ~mask(3), val | mask(3));
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if (cascadeMode) {
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initControlWord++;
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} else {
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cascadeBits = 0;
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initControlWord = 0;
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}
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break;
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case 0x2:
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DPRINTF(I8259, "Received initialization command word 3.\n");
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if (mode == Enums::I8259Master) {
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DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n",
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bits(val, 0) ? " 0" : "",
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bits(val, 1) ? " 1" : "",
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bits(val, 2) ? " 2" : "",
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bits(val, 3) ? " 3" : "",
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bits(val, 4) ? " 4" : "",
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bits(val, 5) ? " 5" : "",
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bits(val, 6) ? " 6" : "",
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bits(val, 7) ? " 7" : "");
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cascadeBits = val;
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} else {
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DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3));
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cascadeBits = val & mask(3);
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}
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if (expectICW4)
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initControlWord++;
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else
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initControlWord = 0;
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break;
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case 0x3:
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DPRINTF(I8259, "Received initialization command word 4.\n");
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if (bits(val, 4)) {
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DPRINTF(I8259, "Special fully nested mode.\n");
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} else {
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DPRINTF(I8259, "Not special fully nested mode.\n");
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}
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if (bits(val, 3) == 0) {
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DPRINTF(I8259, "Nonbuffered.\n");
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} else if (bits(val, 2) == 0) {
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DPRINTF(I8259, "Buffered.\n");
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} else {
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DPRINTF(I8259, "Unrecognized buffer mode.\n");
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}
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DPRINTF(I8259, "%s End Of Interrupt.\n",
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bits(val, 1) ? "Automatic" : "Normal");
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DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
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initControlWord = 0;
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break;
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}
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break;
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}
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return latency;
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}
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void
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X86ISA::I8259::signalInterrupt(int line)
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{
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DPRINTF(I8259, "Interrupt raised on line %d.\n", line);
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if (line > 7)
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fatal("Line number %d doesn't exist. The max is 7.\n");
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if (bits(IMR, line)) {
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DPRINTF(I8259, "Interrupt %d was masked.\n", line);
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} else {
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if (output) {
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DPRINTF(I8259, "Propogating interrupt.\n");
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output->signalInterrupt();
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} else {
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warn("Received interrupt but didn't have "
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"anyone to tell about it.\n");
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}
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}
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}
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X86ISA::I8259 *
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I8259Params::create()
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{
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return new X86ISA::I8259(this);
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}
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