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gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
Andreas Hansson b387d8e213 stats: Update the stats to reflect the 1GHz default system clock 
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
2012-10-25 13:15:59 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.910582 # Number of seconds simulated
sim_ticks 1910582068000 # Number of ticks simulated
final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 942466 # Simulator instruction rate (inst/s)
host_op_rate 942466 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 32082735017 # Simulator tick rate (ticks/s)
host_mem_usage 321492 # Number of bytes of host memory used
host_seconds 59.55 # Real time elapsed on the host
sim_insts 56125446 # Number of instructions simulated
sim_ops 56125446 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7392192 # Number of bytes written to this memory
system.physmem.bytes_written::total 7392192 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
system.physmem.num_reads::total 442975 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115503 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115503 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 445184 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13005193 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1388243 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14838619 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 445184 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 445184 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3869078 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3869078 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3869078 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 445184 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13005193 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1388243 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18707698 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 442975 # Total number of read requests seen
system.physmem.writeReqs 115503 # Total number of write requests seen
system.physmem.cpureqs 559567 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28350400 # Total number of bytes read from memory
system.physmem.bytesWritten 7392192 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28350400 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7392192 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 51 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 28021 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 27576 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 27724 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 27399 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 28096 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 27946 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 27736 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 27622 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 27577 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 27238 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 27723 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 27886 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 27600 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 27483 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 27641 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 27656 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7552 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7244 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 7137 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 6901 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 7584 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7184 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 6832 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7257 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 7441 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7265 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7126 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7165 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7126 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 404 # Number of times wr buffer was full causing retry
system.physmem.totGap 1910570168000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 442975 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 115907 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 130 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 404639 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 7455 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5269 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2334 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2835 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2403 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1793 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2009 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1658 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1931 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1592 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1535 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1623 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1782 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1204 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1459 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 903 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 267 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 130 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 101 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4753 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4845 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4893 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4973 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 4987 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5015 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5021 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5021 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 880 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 269 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 2804911869 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 10779125869 # Sum of mem lat for all requests
system.physmem.totBusLat 1771696000 # Total cycles spent in databus access
system.physmem.totBankLat 6202518000 # Total cycles spent in bank access
system.physmem.avgQLat 6332.72 # Average queueing delay per request
system.physmem.avgBankLat 14003.57 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 24336.29 # Average memory access latency
system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.12 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 14.48 # Average write queue length over time
system.physmem.readRowHits 423327 # Number of row buffer hits during reads
system.physmem.writeRowHits 74914 # Number of row buffer hits during writes
system.physmem.readRowHitRate 95.58 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 64.86 # Row buffer hit rate for writes
system.physmem.avgGap 3421030.31 # Average gap between requests
system.iocache.replacements 41685 # number of replacements
system.iocache.tagsinuse 1.342666 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1745691885000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 1.342666 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.083917 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.083917 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 9475235806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 9475235806 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 9496163804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 9496163804 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 9496163804 # number of overall miss cycles
system.iocache.overall_miss_latency::total 9496163804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228033.206729 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 228033.206729 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 227589.306267 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 227589.306267 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 189601 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 23064 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.220647 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7312468500 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 7312468500 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 7324399500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 7324399500 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 7324399500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 7324399500 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175983.550732 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 175983.550732 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 9055970 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_accesses 728856 # DTB read accesses
system.cpu.dtb.write_hits 6351685 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_accesses 291931 # DTB write accesses
system.cpu.dtb.data_hits 15407655 # DTB hits
system.cpu.dtb.data_misses 11471 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_accesses 1020787 # DTB accesses
system.cpu.itb.fetch_hits 4974178 # ITB hits
system.cpu.itb.fetch_misses 5006 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
system.cpu.itb.fetch_accesses 4979184 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.numCycles 3821164136 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 56125446 # Number of instructions committed
system.cpu.committedOps 56125446 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 51999916 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses
system.cpu.num_func_calls 1482010 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 6463546 # number of instructions that are conditional controls
system.cpu.num_int_insts 51999916 # number of integer instructions
system.cpu.num_fp_insts 324393 # number of float instructions
system.cpu.num_int_register_reads 71242345 # number of times the integer registers were read
system.cpu.num_int_register_writes 38476410 # number of times the integer registers were written
system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read
system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written
system.cpu.num_mem_refs 15460271 # number of memory refs
system.cpu.num_load_insts 9092827 # Number of load instructions
system.cpu.num_store_insts 6367444 # Number of store instructions
system.cpu.num_idle_cycles 3587332264.998123 # Number of idle cycles
system.cpu.num_busy_cycles 233831871.001878 # Number of busy cycles
system.cpu.not_idle_fraction 0.061194 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.938806 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211969 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl
system.cpu.kern.ipl_count::31 106200 57.98% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 183153 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149111 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1855918085500 97.14% 97.14% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 91164500 0.00% 97.14% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 736454000 0.04% 97.18% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 53835630000 2.82% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1910581334000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.814134 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal::swpipl 175936 91.22% 93.42% # number of callpals executed
system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.callpal::total 192878 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches
system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1911
system.cpu.kern.mode_good::user 1741
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch_good::kernel 0.323843 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.392483 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 45587423000 2.39% 2.39% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 5075517000 0.27% 2.65% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1859918392000 97.35% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu.icache.replacements 927460 # number of replacements
system.cpu.icache.tagsinuse 509.121498 # Cycle average of tags in use
system.cpu.icache.total_refs 55209154 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 927971 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 59.494482 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 32120759000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 509.121498 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.994378 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.994378 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 55209154 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 55209154 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 55209154 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 55209154 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 55209154 # number of overall hits
system.cpu.icache.overall_hits::total 55209154 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 928131 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 928131 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 928131 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 928131 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 928131 # number of overall misses
system.cpu.icache.overall_misses::total 928131 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12666318500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12666318500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12666318500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12666318500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12666318500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12666318500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 56137285 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 56137285 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 56137285 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 56137285 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 56137285 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 56137285 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016533 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.016533 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.016533 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.016533 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.016533 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.016533 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13647.123628 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13647.123628 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13647.123628 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13647.123628 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928131 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 928131 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 928131 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 928131 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 928131 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 928131 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10810056500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 10810056500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10810056500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 10810056500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10810056500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 10810056500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016533 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.016533 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.016533 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11647.123628 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11647.123628 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1389800 # number of replacements
system.cpu.dcache.tagsinuse 511.980808 # Cycle average of tags in use
system.cpu.dcache.total_refs 14036386 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1390312 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.095853 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 93442000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.980808 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 7806239 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7806239 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5847887 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5847887 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183020 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 183020 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 13654126 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13654126 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 13654126 # number of overall hits
system.cpu.dcache.overall_hits::total 13654126 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1068876 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1068876 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304232 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304232 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17223 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1373108 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1373108 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1373108 # number of overall misses
system.cpu.dcache.overall_misses::total 1373108 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 22711107000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 22711107000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8598536500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8598536500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 227697000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 227697000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 31309643500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 31309643500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 31309643500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 31309643500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 8875115 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 8875115 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6152119 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6152119 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15027234 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15027234 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15027234 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15027234 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120435 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.120435 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049452 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.049452 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086010 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086010 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::total 21247.653610 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 28263.090339 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 22802.025405 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.ReadReq_mshr_misses::total 1068876 # number of ReadReq MSHR misses
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system.cpu.dcache.LoadLockedReq_mshr_misses::total 17223 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 1373108 # number of overall MSHR misses
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency
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system.cpu.l2cache.tagsinuse 65323.847661 # Cycle average of tags in use
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system.cpu.l2cache.warmup_cycle 5214408002 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks::total 73991 # number of writebacks
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system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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