Andreas Hansson 2a740aa096 Port: Add protocol-agnostic ports in the port hierarchy ... This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default.		2012-10-15 08:12:35 -04:00
..
alpha	Checkpoint: Make system serialize call children	2012-10-15 08:12:29 -04:00
arm	Port: Add protocol-agnostic ports in the port hierarchy	2012-10-15 08:12:35 -04:00
generic	ISA,CPU: Generalize and split out the components of the decode cache.	2012-05-26 13:45:12 -07:00
mips	Checkpoint: Make system serialize call children	2012-10-15 08:12:29 -04:00
noisa	cpu: add separate stats for insts/ops both globally and per cpu model	2012-02-12 16:07:39 -06:00
power	Clock: Add a Cycles wrapper class and use where applicable	2012-08-28 14:30:33 -04:00
sparc	Checkpoint: Make system serialize call children	2012-10-15 08:12:29 -04:00
x86	Port: Add protocol-agnostic ports in the port hierarchy	2012-10-15 08:12:35 -04:00
isa_parser.py	O3: Clean up the O3 structures and try to pack them a bit better.	2012-06-05 01:23:09 -04:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	CPU: Merge the predecoder and decoder.	2012-05-26 13:44:46 -07:00