gem5/src/cpu/simple
Joel Hestness 52b6119228 TimingSimpleCPU: split data sender state fix
In sendSplitData, keep a pointer to the senderState that may be updated after
the call to handle*Packet. This way, if the receiver updates the packet
senderState, it can still be accessed in sendSplitData.
2011-02-06 22:14:18 -08:00
..
atomic.cc mcpat: Adds McPAT performance counters 2011-02-06 22:14:17 -08:00
atomic.hh CPU: Add readBytes and writeBytes functions to the exec contexts. 2010-08-13 06:16:02 -07:00
AtomicSimpleCPU.py Config: Keep track of uncached and cached ports separately. 2011-02-03 20:23:00 -08:00
base.cc mcpat: Adds McPAT performance counters 2011-02-06 22:14:17 -08:00
base.hh mcpat: Adds McPAT performance counters 2011-02-06 22:14:17 -08:00
BaseSimpleCPU.py params: Convert the CPU objects to use the auto generated param structs. 2008-08-11 12:22:16 -07:00
SConscript params: Convert the CPU objects to use the auto generated param structs. 2008-08-11 12:22:16 -07:00
SConsopts cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
timing.cc TimingSimpleCPU: split data sender state fix 2011-02-06 22:14:18 -08:00
timing.hh CPU: Fix bug when a split transaction is issued to a faster cache 2010-11-15 14:04:03 -06:00
TimingSimpleCPU.py Config: Keep track of uncached and cached ports separately. 2011-02-03 20:23:00 -08:00