52b31ea0a6
#include changes. --HG-- rename : sim/cache/lzss_compression.cc => base/compression/lzss_compression.cc rename : sim/cache/lzss_compression.hh => base/compression/lzss_compression.hh rename : sim/cache/null_compression.hh => base/compression/null_compression.hh rename : sim/hybrid_pred.cc => base/hybrid_pred.cc rename : sim/hybrid_pred.hh => base/hybrid_pred.hh rename : base/aout_object.cc => base/loader/aout_object.cc rename : base/aout_object.hh => base/loader/aout_object.hh rename : base/coff_sym.h => base/loader/coff_sym.h rename : base/coff_symconst.h => base/loader/coff_symconst.h rename : base/ecoff_object.cc => base/loader/ecoff_object.cc rename : base/ecoff_object.hh => base/loader/ecoff_object.hh rename : base/elf_object.cc => base/loader/elf_object.cc rename : base/elf_object.hh => base/loader/elf_object.hh rename : base/exec_aout.h => base/loader/exec_aout.h rename : base/exec_ecoff.h => base/loader/exec_ecoff.h rename : base/object_file.cc => base/loader/object_file.cc rename : base/object_file.hh => base/loader/object_file.hh rename : base/symtab.cc => base/loader/symtab.cc rename : base/symtab.hh => base/loader/symtab.hh rename : sim/predictor.hh => base/predictor.hh rename : sim/sat_counter.cc => base/sat_counter.cc rename : sim/sat_counter.hh => base/sat_counter.hh rename : sim/base_cpu.cc => cpu/base_cpu.cc rename : sim/base_cpu.hh => cpu/base_cpu.hh rename : sim/exec_context.cc => cpu/exec_context.cc rename : sim/exec_context.hh => cpu/exec_context.hh rename : sim/exetrace.cc => cpu/exetrace.cc rename : sim/exetrace.hh => cpu/exetrace.hh rename : sim/op_class.hh => cpu/full_cpu/op_class.hh rename : sim/smt.hh => cpu/full_cpu/smt.hh rename : sim/inst_seq.hh => cpu/inst_seq.hh rename : sim/intr_control.cc => cpu/intr_control.cc rename : sim/intr_control.hh => cpu/intr_control.hh rename : sim/memtest.cc => cpu/memtest/memtest.cc rename : sim/memtest.hh => cpu/memtest/memtest.hh rename : sim/pc_event.cc => cpu/pc_event.cc rename : sim/pc_event.hh => cpu/pc_event.hh rename : sim/simple_cpu.cc => cpu/simple_cpu/simple_cpu.cc rename : sim/simple_cpu.hh => cpu/simple_cpu/simple_cpu.hh rename : sim/static_inst.cc => cpu/static_inst.cc rename : sim/static_inst.hh => cpu/static_inst.hh extra : convert_revision : 05bd41acb2a424f1a38609fd4ac6df681bb479d6
746 lines
19 KiB
C++
746 lines
19 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <iostream>
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#include <iomanip>
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#include <list>
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#include <sstream>
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#include <string>
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#include <stdio.h>
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#include <stdlib.h>
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#include <math.h>
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#include "host.hh"
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#include "cprintf.hh"
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#include "misc.hh"
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#include "smt.hh"
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#include "annotation.hh"
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#include "exec_context.hh"
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#include "base_cpu.hh"
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#include "debug.hh"
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#include "simple_cpu.hh"
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#include "inifile.hh"
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#include "mem_interface.hh"
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#include "base_mem.hh"
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#include "static_inst.hh"
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#ifdef FULL_SYSTEM
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#include "memory_control.hh"
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#include "physical_memory.hh"
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#include "alpha_memory.hh"
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#include "system.hh"
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#else // !FULL_SYSTEM
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#include "functional_memory.hh"
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#include "prog.hh"
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#include "eio.hh"
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#endif // FULL_SYSTEM
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#include "exetrace.hh"
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#include "trace.hh"
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#include "sim_events.hh"
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#include "pollevent.hh"
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#include "sim_object.hh"
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#include "sim_stats.hh"
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#include "range.hh"
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#include "symtab.hh"
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#ifdef FULL_SYSTEM
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#include "vtophys.hh"
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#include "pciareg.h"
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#include "remote_gdb.hh"
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#include "alpha_access.h"
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#endif
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using namespace std;
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SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
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: Event(&mainEventQueue),
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cpu(_cpu)
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{
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}
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void SimpleCPU::CacheCompletionEvent::process()
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{
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cpu->processCacheCompletion();
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}
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const char *
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SimpleCPU::CacheCompletionEvent::description()
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{
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return "cache completion event";
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}
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#ifdef FULL_SYSTEM
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SimpleCPU::SimpleCPU(const string &_name,
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System *_system,
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Counter max_insts_any_thread,
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Counter max_insts_all_threads,
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AlphaItb *itb, AlphaDtb *dtb,
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FunctionalMemory *mem,
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MemInterface *icache_interface,
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MemInterface *dcache_interface,
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int cpu_id, Tick freq)
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: BaseCPU(_name, /* number_of_threads */ 1,
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max_insts_any_thread, max_insts_all_threads,
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_system, cpu_id, freq),
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#else
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SimpleCPU::SimpleCPU(const string &_name, Process *_process,
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Counter max_insts_any_thread,
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Counter max_insts_all_threads,
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MemInterface *icache_interface,
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MemInterface *dcache_interface)
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: BaseCPU(_name, /* number_of_threads */ 1,
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max_insts_any_thread, max_insts_all_threads),
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#endif
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tickEvent(this), xc(NULL), cacheCompletionEvent(this)
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{
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#ifdef FULL_SYSTEM
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xc = new ExecContext(this, 0, system, itb, dtb, mem, cpu_id);
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_status = Running;
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if (cpu_id != 0) {
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xc->setStatus(ExecContext::Unallocated);
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//Open a GDB debug session on port (7000 + the cpu_id)
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(new GDBListener(new RemoteGDB(system, xc), 7000 + cpu_id))->listen();
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AlphaISA::init(system->physmem, &xc->regs);
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fault = Reset_Fault;
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IntReg *ipr = xc->regs.ipr;
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ipr[TheISA::IPR_MCSR] = 0x6;
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AlphaISA::swap_palshadow(&xc->regs, true);
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xc->regs.pc =
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ipr[TheISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
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xc->regs.npc = xc->regs.pc + sizeof(MachInst);
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_status = Idle;
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}
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else {
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system->initBootContext(xc);
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// Reset the system
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//
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AlphaISA::init(system->physmem, &xc->regs);
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fault = Reset_Fault;
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IntReg *ipr = xc->regs.ipr;
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ipr[TheISA::IPR_MCSR] = 0x6;
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AlphaISA::swap_palshadow(&xc->regs, true);
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xc->regs.pc = ipr[TheISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
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xc->regs.npc = xc->regs.pc + sizeof(MachInst);
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_status = Running;
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tickEvent.schedule(0);
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}
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#else
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xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
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fault = No_Fault;
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if (xc->status() == ExecContext::Active) {
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_status = Running;
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tickEvent.schedule(0);
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} else
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_status = Idle;
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#endif // !FULL_SYSTEM
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icacheInterface = icache_interface;
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dcacheInterface = dcache_interface;
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memReq = new MemReq();
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memReq->xc = xc;
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memReq->asid = 0;
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numInst = 0;
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last_idle = 0;
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lastIcacheStall = 0;
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lastDcacheStall = 0;
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contexts.push_back(xc);
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}
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SimpleCPU::~SimpleCPU()
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{
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}
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void
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SimpleCPU::regStats()
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{
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BaseCPU::regStats();
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numInsts
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.name(name() + ".num_insts")
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.desc("Number of instructions executed")
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;
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numMemRefs
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.name(name() + ".num_refs")
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.desc("Number of memory references")
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;
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idleCycles
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.name(name() + ".idle_cycles")
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.desc("Number of idle cycles")
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;
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idleFraction
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.name(name() + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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icacheStallCycles
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.name(name() + ".icache_stall_cycles")
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.desc("ICache total stall cycles")
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.prereq(icacheStallCycles)
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;
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dcacheStallCycles
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.name(name() + ".dcache_stall_cycles")
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.desc("DCache total stall cycles")
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.prereq(dcacheStallCycles)
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;
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idleFraction = idleCycles / simTicks;
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numInsts = Statistics::scalar(numInst);
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simInsts += numInsts;
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}
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void
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SimpleCPU::serialize()
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{
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nameOut();
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#ifdef FULL_SYSTEM
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#if 0
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// do we need this anymore?? egh
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childOut("itb", xc->itb);
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childOut("dtb", xc->dtb);
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childOut("physmem", physmem);
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#endif
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#endif
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for (int i = 0; i < NumIntRegs; i++) {
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stringstream buf;
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ccprintf(buf, "R%02d", i);
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paramOut(buf.str(), xc->regs.intRegFile[i]);
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}
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for (int i = 0; i < NumFloatRegs; i++) {
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stringstream buf;
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ccprintf(buf, "F%02d", i);
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paramOut(buf.str(), xc->regs.floatRegFile.d[i]);
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}
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// CPUTraitsType::serializeSpecialRegs(getProxy(), xc->regs);
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}
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void
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SimpleCPU::unserialize(IniFile &db, const string &category, ConfigNode *node)
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{
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string data;
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for (int i = 0; i < NumIntRegs; i++) {
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stringstream buf;
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ccprintf(buf, "R%02d", i);
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db.findDefault(category, buf.str(), data);
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to_number(data,xc->regs.intRegFile[i]);
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}
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for (int i = 0; i < NumFloatRegs; i++) {
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stringstream buf;
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ccprintf(buf, "F%02d", i);
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db.findDefault(category, buf.str(), data);
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xc->regs.floatRegFile.d[i] = strtod(data.c_str(),NULL);
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}
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// Read in Special registers
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// CPUTraitsType::unserializeSpecialRegs(db,category,node,xc->regs);
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}
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void
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change_thread_state(int thread_number, int activate, int priority)
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{
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}
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// precise architected memory state accessor macros
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template <class T>
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Fault
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SimpleCPU::read(Addr addr, T& data, unsigned flags)
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{
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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Fault fault = xc->translateDataReadReq(memReq);
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// do functional access
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if (fault == No_Fault)
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fault = xc->read(memReq, data);
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if (traceData) {
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traceData->setAddr(addr);
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if (fault == No_Fault)
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traceData->setData(data);
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}
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// if we have a cache, do cache access too
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if (fault == No_Fault && dcacheInterface) {
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memReq->cmd = Read;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~UNCACHEABLE;
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && dcacheInterface->doEvents) {
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memReq->completionEvent = &cacheCompletionEvent;
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setStatus(DcacheMissStall);
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}
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}
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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SimpleCPU::read(Addr addr, uint64_t& data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint32_t& data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint16_t& data, unsigned flags);
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template
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Fault
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SimpleCPU::read(Addr addr, uint8_t& data, unsigned flags);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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SimpleCPU::read(Addr addr, double& data, unsigned flags)
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{
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return read(addr, *(uint64_t*)&data, flags);
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}
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template<>
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Fault
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SimpleCPU::read(Addr addr, float& data, unsigned flags)
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{
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return read(addr, *(uint32_t*)&data, flags);
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}
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template<>
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Fault
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SimpleCPU::read(Addr addr, int32_t& data, unsigned flags)
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{
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return read(addr, (uint32_t&)data, flags);
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}
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template <class T>
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Fault
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SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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if (traceData) {
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traceData->setAddr(addr);
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traceData->setData(data);
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}
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memReq->reset(addr, sizeof(T), flags);
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// translate to physical address
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Fault fault = xc->translateDataWriteReq(memReq);
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// do functional access
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if (fault == No_Fault)
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fault = xc->write(memReq, data);
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if (fault == No_Fault && dcacheInterface) {
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memReq->cmd = Write;
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memReq->data = (uint8_t *)&data;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~UNCACHEABLE;
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && dcacheInterface->doEvents) {
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memReq->completionEvent = &cacheCompletionEvent;
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setStatus(DcacheMissStall);
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}
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}
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if (res && (fault == No_Fault))
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*res = memReq->result;
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
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template
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Fault
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SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint64_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint32_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write((uint32_t)data, addr, flags, res);
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}
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#ifdef FULL_SYSTEM
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Addr
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SimpleCPU::dbg_vtophys(Addr addr)
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{
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return vtophys(xc, addr);
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}
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#endif // FULL_SYSTEM
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Tick save_cycle = 0;
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void
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SimpleCPU::processCacheCompletion()
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{
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switch (status()) {
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case IcacheMissStall:
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icacheStallCycles += curTick - lastIcacheStall;
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setStatus(IcacheMissComplete);
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break;
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case DcacheMissStall:
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dcacheStallCycles += curTick - lastDcacheStall;
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setStatus(Running);
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break;
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default:
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panic("SimpleCPU::processCacheCompletion: bad state");
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break;
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}
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}
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#ifdef FULL_SYSTEM
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void
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SimpleCPU::post_interrupt(int int_num, int index)
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{
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BaseCPU::post_interrupt(int_num, index);
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if (xc->status() == ExecContext::Suspended) {
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DPRINTF(IPI,"Suspended Processor awoke\n");
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xc->setStatus(ExecContext::Active);
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Annotate::Resume(xc);
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}
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}
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#endif // FULL_SYSTEM
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/* start simulation, program loaded, processor precise state initialized */
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void
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SimpleCPU::tick()
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{
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traceData = NULL;
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#ifdef FULL_SYSTEM
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if (fault == No_Fault && AlphaISA::check_interrupts &&
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xc->cpu->check_interrupts() &&
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!PC_PAL(xc->regs.pc) &&
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status() != IcacheMissComplete) {
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int ipl = 0;
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int summary = 0;
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AlphaISA::check_interrupts = 0;
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IntReg *ipr = xc->regs.ipr;
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if (xc->regs.ipr[TheISA::IPR_SIRR]) {
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for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
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i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
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if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
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// See table 4-19 of 21164 hardware reference
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ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
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summary |= (ULL(1) << i);
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}
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}
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}
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uint64_t interrupts = xc->cpu->intr_status();
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for(int i = TheISA::INTLEVEL_EXTERNAL_MIN;
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i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
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if (interrupts & (ULL(1) << i)) {
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// See table 4-19 of 21164 hardware reference
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ipl = i;
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summary |= (ULL(1) << i);
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}
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}
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if (ipr[TheISA::IPR_ASTRR])
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panic("asynchronous traps not implemented\n");
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if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
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ipr[TheISA::IPR_ISR] = summary;
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ipr[TheISA::IPR_INTID] = ipl;
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xc->ev5_trap(Interrupt_Fault);
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DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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ipr[TheISA::IPR_IPLR], ipl, summary);
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}
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}
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#endif
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// maintain $r0 semantics
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xc->regs.intRegFile[ZeroReg] = 0;
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#ifdef TARGET_ALPHA
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xc->regs.floatRegFile.d[ZeroReg] = 0.0;
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#endif // TARGET_ALPHA
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if (status() == IcacheMissComplete) {
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// We've already fetched an instruction and were stalled on an
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// I-cache miss. No need to fetch it again.
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setStatus(Running);
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}
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else {
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// Try to fetch an instruction
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// set up memory request for instruction fetch
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#ifdef FULL_SYSTEM
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#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
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#else
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#define IFETCH_FLAGS(pc) 0
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#endif
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memReq->cmd = Read;
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memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
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IFETCH_FLAGS(xc->regs.pc));
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fault = xc->translateInstReq(memReq);
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if (fault == No_Fault)
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fault = xc->mem->read(memReq, inst);
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if (icacheInterface && fault == No_Fault) {
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~UNCACHEABLE;
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MemAccessResult result = icacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && icacheInterface->doEvents) {
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memReq->completionEvent = &cacheCompletionEvent;
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setStatus(IcacheMissStall);
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return;
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}
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}
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}
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// If we've got a valid instruction (i.e., no fault on instruction
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// fetch), then execute it.
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if (fault == No_Fault) {
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// keep an instruction count
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numInst++;
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// check for instruction-count-based events
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comInsnEventQueue[0]->serviceEvents(numInst);
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// decode the instruction
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StaticInstPtr<TheISA> si(inst);
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traceData = Trace::getInstRecord(curTick, xc, this, si,
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xc->regs.pc);
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#ifdef FULL_SYSTEM
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xc->regs.opcode = (inst >> 26) & 0x3f;
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xc->regs.ra = (inst >> 21) & 0x1f;
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#endif // FULL_SYSTEM
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xc->func_exe_insn++;
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fault = si->execute(this, xc, traceData);
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if (si->isMemRef()) {
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numMemRefs++;
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}
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if (traceData)
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traceData->finalize();
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} // if (fault == No_Fault)
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if (fault != No_Fault) {
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#ifdef FULL_SYSTEM
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xc->ev5_trap(fault);
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#else // !FULL_SYSTEM
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fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
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#endif // FULL_SYSTEM
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}
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else {
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// go to the next instruction
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xc->regs.pc = xc->regs.npc;
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xc->regs.npc += sizeof(MachInst);
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}
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#ifdef FULL_SYSTEM
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Addr oldpc;
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do {
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oldpc = xc->regs.pc;
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system->pcEventQueue.service(xc);
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} while (oldpc != xc->regs.pc);
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#endif
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assert(status() == Running ||
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status() == Idle ||
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status() == DcacheMissStall);
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if (status() == Running && !tickEvent.scheduled())
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tickEvent.schedule(curTick + 1);
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}
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|
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////////////////////////////////////////////////////////////////////////
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//
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// SimpleCPU Simulation Object
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//
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
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Param<Counter> max_insts_any_thread;
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Param<Counter> max_insts_all_threads;
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#ifdef FULL_SYSTEM
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SimObjectParam<AlphaItb *> itb;
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SimObjectParam<AlphaDtb *> dtb;
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SimObjectParam<FunctionalMemory *> mem;
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SimObjectParam<System *> system;
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Param<int> cpu_id;
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Param<int> mult;
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#else
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SimObjectParam<Process *> workload;
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#endif // FULL_SYSTEM
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SimObjectParam<BaseMem *> icache;
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SimObjectParam<BaseMem *> dcache;
|
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END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
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BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
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INIT_PARAM_DFLT(max_insts_any_thread,
|
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"terminate when any thread reaches this insn count",
|
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0),
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INIT_PARAM_DFLT(max_insts_all_threads,
|
|
"terminate when all threads have reached this insn count",
|
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0),
|
|
|
|
#ifdef FULL_SYSTEM
|
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INIT_PARAM(itb, "Instruction TLB"),
|
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INIT_PARAM(dtb, "Data TLB"),
|
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INIT_PARAM(mem, "memory"),
|
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INIT_PARAM(system, "system object"),
|
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INIT_PARAM_DFLT(cpu_id, "CPU identification number", 0),
|
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INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
|
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#else
|
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INIT_PARAM(workload, "processes to run"),
|
|
#endif // FULL_SYSTEM
|
|
|
|
INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
|
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INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
|
|
CREATE_SIM_OBJECT(SimpleCPU)
|
|
{
|
|
#ifdef FULL_SYSTEM
|
|
if (mult != 1)
|
|
panic("processor clock multiplier must be 1\n");
|
|
|
|
return new SimpleCPU(getInstanceName(), system,
|
|
max_insts_any_thread, max_insts_all_threads,
|
|
itb, dtb, mem,
|
|
(icache) ? icache->getInterface() : NULL,
|
|
(dcache) ? dcache->getInterface() : NULL,
|
|
cpu_id, ticksPerSecond * mult);
|
|
#else
|
|
|
|
return new SimpleCPU(getInstanceName(), workload,
|
|
max_insts_any_thread, max_insts_all_threads,
|
|
icache->getInterface(), dcache->getInterface());
|
|
|
|
#endif // FULL_SYSTEM
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
|