52b31ea0a6
#include changes. --HG-- rename : sim/cache/lzss_compression.cc => base/compression/lzss_compression.cc rename : sim/cache/lzss_compression.hh => base/compression/lzss_compression.hh rename : sim/cache/null_compression.hh => base/compression/null_compression.hh rename : sim/hybrid_pred.cc => base/hybrid_pred.cc rename : sim/hybrid_pred.hh => base/hybrid_pred.hh rename : base/aout_object.cc => base/loader/aout_object.cc rename : base/aout_object.hh => base/loader/aout_object.hh rename : base/coff_sym.h => base/loader/coff_sym.h rename : base/coff_symconst.h => base/loader/coff_symconst.h rename : base/ecoff_object.cc => base/loader/ecoff_object.cc rename : base/ecoff_object.hh => base/loader/ecoff_object.hh rename : base/elf_object.cc => base/loader/elf_object.cc rename : base/elf_object.hh => base/loader/elf_object.hh rename : base/exec_aout.h => base/loader/exec_aout.h rename : base/exec_ecoff.h => base/loader/exec_ecoff.h rename : base/object_file.cc => base/loader/object_file.cc rename : base/object_file.hh => base/loader/object_file.hh rename : base/symtab.cc => base/loader/symtab.cc rename : base/symtab.hh => base/loader/symtab.hh rename : sim/predictor.hh => base/predictor.hh rename : sim/sat_counter.cc => base/sat_counter.cc rename : sim/sat_counter.hh => base/sat_counter.hh rename : sim/base_cpu.cc => cpu/base_cpu.cc rename : sim/base_cpu.hh => cpu/base_cpu.hh rename : sim/exec_context.cc => cpu/exec_context.cc rename : sim/exec_context.hh => cpu/exec_context.hh rename : sim/exetrace.cc => cpu/exetrace.cc rename : sim/exetrace.hh => cpu/exetrace.hh rename : sim/op_class.hh => cpu/full_cpu/op_class.hh rename : sim/smt.hh => cpu/full_cpu/smt.hh rename : sim/inst_seq.hh => cpu/inst_seq.hh rename : sim/intr_control.cc => cpu/intr_control.cc rename : sim/intr_control.hh => cpu/intr_control.hh rename : sim/memtest.cc => cpu/memtest/memtest.cc rename : sim/memtest.hh => cpu/memtest/memtest.hh rename : sim/pc_event.cc => cpu/pc_event.cc rename : sim/pc_event.hh => cpu/pc_event.hh rename : sim/simple_cpu.cc => cpu/simple_cpu/simple_cpu.cc rename : sim/simple_cpu.hh => cpu/simple_cpu/simple_cpu.hh rename : sim/static_inst.cc => cpu/static_inst.cc rename : sim/static_inst.hh => cpu/static_inst.hh extra : convert_revision : 05bd41acb2a424f1a38609fd4ac6df681bb479d6
231 lines
5.9 KiB
C++
231 lines
5.9 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <algorithm>
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#include <map>
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#include <string>
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#include <utility>
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#include "debug.hh"
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#include "exec_context.hh"
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#include "pc_event.hh"
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#include "trace.hh"
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#include "universe.hh"
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#ifdef FULL_SYSTEM
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#include "arguments.hh"
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#include "pmap.h"
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#include "kernel.hh"
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#include "memory_control.hh"
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#include "cpu.hh"
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#include "system.hh"
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#include "bpred.hh"
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#endif
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using namespace std;
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PCEventQueue::PCEventQueue()
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{}
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PCEventQueue::~PCEventQueue()
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{}
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bool
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PCEventQueue::remove(PCEvent *event)
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{
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int removed = 0;
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range_t range = equal_range(event);
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for (iterator i = range.first; i != range.second; ++i) {
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if (*i == event) {
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DPRINTF(PCEvent, "PC based event removed at %#x: %s\n",
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event->pc(), event->descr());
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pc_map.erase(i);
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++removed;
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}
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}
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return removed > 0;
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}
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bool
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PCEventQueue::schedule(PCEvent *event)
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{
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pc_map.push_back(event);
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sort(pc_map.begin(), pc_map.end(), MapCompare());
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DPRINTF(PCEvent, "PC based event scheduled for %#x: %s\n",
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event->pc(), event->descr());
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return true;
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}
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bool
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PCEventQueue::service(ExecContext *xc)
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{
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Addr pc = xc->regs.pc;
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int serviced = 0;
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range_t range = equal_range(pc);
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for (iterator i = range.first; i != range.second; ++i) {
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// Make sure that the pc wasn't changed as the side effect of
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// another event. This for example, prevents two invocations
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// of the SkipFuncEvent. Maybe we should have separate PC
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// event queues for each processor?
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if (pc != xc->regs.pc)
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continue;
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DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n",
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(*i)->pc(), (*i)->descr());
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(*i)->process(xc);
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++serviced;
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}
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return serviced > 0;
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}
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void
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PCEventQueue::dump() const
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{
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const_iterator i = pc_map.begin();
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const_iterator e = pc_map.end();
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for (; i != e; ++i)
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cprintf("%d: event at %#x: %s\n", curTick, (*i)->pc(),
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(*i)->descr());
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}
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PCEventQueue::range_t
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PCEventQueue::equal_range(Addr pc)
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{
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return std::equal_range(pc_map.begin(), pc_map.end(), pc, MapCompare());
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}
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#ifdef FULL_SYSTEM
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void
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SkipFuncEvent::process(ExecContext *xc)
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{
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Addr newpc = xc->regs.intRegFile[ReturnAddressReg];
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DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description,
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xc->regs.pc, newpc);
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xc->regs.pc = newpc;
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xc->regs.npc = xc->regs.pc + sizeof(MachInst);
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BranchPred *bp = xc->cpu->getBranchPred();
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if (bp != NULL) {
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bp->popRAS(xc->thread_num);
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}
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}
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void
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BadAddrEvent::process(ExecContext *xc)
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{
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// The following gross hack is the equivalent function to the
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// annotation for vmunix::badaddr in:
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// simos/simulation/apps/tcl/osf/tlaser.tcl
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uint64_t a0 = xc->regs.intRegFile[ArgumentReg0];
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if (a0 < ALPHA_K0SEG_BASE || a0 >= ALPHA_K1SEG_BASE ||
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xc->memCtrl->badaddr(ALPHA_K0SEG_TO_PHYS(a0) & PA_IMPL_MASK)) {
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DPRINTF(BADADDR, "badaddr arg=%#x bad\n", a0);
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xc->regs.intRegFile[ReturnValueReg] = 0x1;
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SkipFuncEvent::process(xc);
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}
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else
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DPRINTF(BADADDR, "badaddr arg=%#x good\n", a0);
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}
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void
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PrintfEvent::process(ExecContext *xc)
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{
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if (DTRACE(Printf)) {
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DebugOut() << curTick << ": " << xc->cpu->name() << ": ";
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AlphaArguments args(xc);
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Kernel::Printf(args);
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}
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}
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void
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DebugPrintfEvent::process(ExecContext *xc)
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{
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if (DTRACE(DebugPrintf)) {
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if (!raw)
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DebugOut() << curTick << ": " << xc->cpu->name() << ": ";
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AlphaArguments args(xc);
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Kernel::Printf(args);
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}
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}
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void
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DumpMbufEvent::process(ExecContext *xc)
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{
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if (DTRACE(DebugPrintf)) {
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AlphaArguments args(xc);
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Kernel::DumpMbuf(args);
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}
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}
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#endif
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BreakPCEvent::BreakPCEvent(PCEventQueue *q, const std::string &desc, bool del)
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: PCEvent(q, desc), remove(del)
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{
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}
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void
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BreakPCEvent::process(ExecContext *xc)
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{
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debug_break();
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if (remove)
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delete this;
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}
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#ifdef FULL_SYSTEM
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extern "C"
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void
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sched_break_pc_sys(System *sys, Addr addr)
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{
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PCEvent *event = new BreakPCEvent(&sys->pcEventQueue, "debug break", true);
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event->schedule(addr);
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}
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extern "C"
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void
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sched_break_pc(Addr addr)
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{
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for (vector<System *>::iterator sysi = System::systemList.begin();
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sysi != System::systemList.end(); ++sysi) {
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sched_break_pc_sys(*sysi, addr);
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}
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}
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#endif
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