gem5/cpu/memtest/memtest.hh
Steve Reinhardt 52b31ea0a6 File moves for the reorg. Tree is in broken state until I commit the makefile and
#include changes.

--HG--
rename : sim/cache/lzss_compression.cc => base/compression/lzss_compression.cc
rename : sim/cache/lzss_compression.hh => base/compression/lzss_compression.hh
rename : sim/cache/null_compression.hh => base/compression/null_compression.hh
rename : sim/hybrid_pred.cc => base/hybrid_pred.cc
rename : sim/hybrid_pred.hh => base/hybrid_pred.hh
rename : base/aout_object.cc => base/loader/aout_object.cc
rename : base/aout_object.hh => base/loader/aout_object.hh
rename : base/coff_sym.h => base/loader/coff_sym.h
rename : base/coff_symconst.h => base/loader/coff_symconst.h
rename : base/ecoff_object.cc => base/loader/ecoff_object.cc
rename : base/ecoff_object.hh => base/loader/ecoff_object.hh
rename : base/elf_object.cc => base/loader/elf_object.cc
rename : base/elf_object.hh => base/loader/elf_object.hh
rename : base/exec_aout.h => base/loader/exec_aout.h
rename : base/exec_ecoff.h => base/loader/exec_ecoff.h
rename : base/object_file.cc => base/loader/object_file.cc
rename : base/object_file.hh => base/loader/object_file.hh
rename : base/symtab.cc => base/loader/symtab.cc
rename : base/symtab.hh => base/loader/symtab.hh
rename : sim/predictor.hh => base/predictor.hh
rename : sim/sat_counter.cc => base/sat_counter.cc
rename : sim/sat_counter.hh => base/sat_counter.hh
rename : sim/base_cpu.cc => cpu/base_cpu.cc
rename : sim/base_cpu.hh => cpu/base_cpu.hh
rename : sim/exec_context.cc => cpu/exec_context.cc
rename : sim/exec_context.hh => cpu/exec_context.hh
rename : sim/exetrace.cc => cpu/exetrace.cc
rename : sim/exetrace.hh => cpu/exetrace.hh
rename : sim/op_class.hh => cpu/full_cpu/op_class.hh
rename : sim/smt.hh => cpu/full_cpu/smt.hh
rename : sim/inst_seq.hh => cpu/inst_seq.hh
rename : sim/intr_control.cc => cpu/intr_control.cc
rename : sim/intr_control.hh => cpu/intr_control.hh
rename : sim/memtest.cc => cpu/memtest/memtest.cc
rename : sim/memtest.hh => cpu/memtest/memtest.hh
rename : sim/pc_event.cc => cpu/pc_event.cc
rename : sim/pc_event.hh => cpu/pc_event.hh
rename : sim/simple_cpu.cc => cpu/simple_cpu/simple_cpu.cc
rename : sim/simple_cpu.hh => cpu/simple_cpu/simple_cpu.hh
rename : sim/static_inst.cc => cpu/static_inst.cc
rename : sim/static_inst.hh => cpu/static_inst.hh
extra : convert_revision : 05bd41acb2a424f1a38609fd4ac6df681bb479d6
2003-10-10 09:57:26 -07:00

141 lines
4 KiB
C++

/*
* Copyright (c) 2003 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MEMTEST_HH__
#define __MEMTEST_HH__
#include "sim_object.hh"
#include "mem_interface.hh"
#include "functional_memory.hh"
#include "base_cpu.hh"
#include "exec_context.hh"
#include "statistics.hh"
#include "sim_stats.hh"
class MemTest : public BaseCPU
{
public:
MemTest(const std::string &name,
MemInterface *_cache_interface,
FunctionalMemory *main_mem,
FunctionalMemory *check_mem,
unsigned _memorySize,
unsigned _percentReads,
unsigned _percentUncacheable,
unsigned _maxReads,
unsigned _progressInterval,
Addr _traceAddr);
// register statistics
virtual void regStats();
// main simulation loop (one cycle)
void tick();
protected:
class TickEvent : public Event
{
private:
MemTest *cpu;
public:
TickEvent(MemTest *c)
: Event(&mainEventQueue, 100), cpu(c) {}
void process() {cpu->tick();}
virtual const char *description() { return "tick event"; }
};
TickEvent tickEvent;
MemInterface *cacheInterface;
FunctionalMemory *mainMem;
FunctionalMemory *checkMem;
ExecContext *xc;
unsigned size; // size of testing memory region
unsigned percentReads; // target percentage of read accesses
unsigned percentUncacheable;
Tick maxReads; // max # of reads to perform (then quit)
unsigned blockSize;
Addr blockAddrMask;
Addr blockAddr(Addr addr)
{
return (addr & ~blockAddrMask);
}
Addr traceBlockAddr;
Addr baseAddr1; // fix this to option
Addr baseAddr2; // fix this to option
Addr uncacheAddr;
unsigned progressInterval; // frequency of progress reports
Tick nextProgressMessage; // access # for next progress report
Tick noResponseCycles;
Statistics::Scalar<long long int> numReads;
Statistics::Scalar<long long int> numWrites;
Statistics::Scalar<long long int> numCopies;
// called by MemCompleteEvent::process()
void completeRequest(MemReqPtr req, uint8_t *data);
friend class MemCompleteEvent;
};
class MemCompleteEvent : public Event
{
MemReqPtr req;
uint8_t *data;
MemTest *tester;
public:
MemCompleteEvent(MemReqPtr _req, uint8_t *_data, MemTest *_tester)
: Event(&mainEventQueue),
req(_req), data(_data), tester(_tester)
{
}
void process();
virtual const char *description();
};
#endif // __MEMTEST_HH__