52b31ea0a6
#include changes. --HG-- rename : sim/cache/lzss_compression.cc => base/compression/lzss_compression.cc rename : sim/cache/lzss_compression.hh => base/compression/lzss_compression.hh rename : sim/cache/null_compression.hh => base/compression/null_compression.hh rename : sim/hybrid_pred.cc => base/hybrid_pred.cc rename : sim/hybrid_pred.hh => base/hybrid_pred.hh rename : base/aout_object.cc => base/loader/aout_object.cc rename : base/aout_object.hh => base/loader/aout_object.hh rename : base/coff_sym.h => base/loader/coff_sym.h rename : base/coff_symconst.h => base/loader/coff_symconst.h rename : base/ecoff_object.cc => base/loader/ecoff_object.cc rename : base/ecoff_object.hh => base/loader/ecoff_object.hh rename : base/elf_object.cc => base/loader/elf_object.cc rename : base/elf_object.hh => base/loader/elf_object.hh rename : base/exec_aout.h => base/loader/exec_aout.h rename : base/exec_ecoff.h => base/loader/exec_ecoff.h rename : base/object_file.cc => base/loader/object_file.cc rename : base/object_file.hh => base/loader/object_file.hh rename : base/symtab.cc => base/loader/symtab.cc rename : base/symtab.hh => base/loader/symtab.hh rename : sim/predictor.hh => base/predictor.hh rename : sim/sat_counter.cc => base/sat_counter.cc rename : sim/sat_counter.hh => base/sat_counter.hh rename : sim/base_cpu.cc => cpu/base_cpu.cc rename : sim/base_cpu.hh => cpu/base_cpu.hh rename : sim/exec_context.cc => cpu/exec_context.cc rename : sim/exec_context.hh => cpu/exec_context.hh rename : sim/exetrace.cc => cpu/exetrace.cc rename : sim/exetrace.hh => cpu/exetrace.hh rename : sim/op_class.hh => cpu/full_cpu/op_class.hh rename : sim/smt.hh => cpu/full_cpu/smt.hh rename : sim/inst_seq.hh => cpu/inst_seq.hh rename : sim/intr_control.cc => cpu/intr_control.cc rename : sim/intr_control.hh => cpu/intr_control.hh rename : sim/memtest.cc => cpu/memtest/memtest.cc rename : sim/memtest.hh => cpu/memtest/memtest.hh rename : sim/pc_event.cc => cpu/pc_event.cc rename : sim/pc_event.hh => cpu/pc_event.hh rename : sim/simple_cpu.cc => cpu/simple_cpu/simple_cpu.cc rename : sim/simple_cpu.hh => cpu/simple_cpu/simple_cpu.hh rename : sim/static_inst.cc => cpu/static_inst.cc rename : sim/static_inst.hh => cpu/static_inst.hh extra : convert_revision : 05bd41acb2a424f1a38609fd4ac6df681bb479d6
141 lines
4 KiB
C++
141 lines
4 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEMTEST_HH__
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#define __MEMTEST_HH__
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#include "sim_object.hh"
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#include "mem_interface.hh"
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#include "functional_memory.hh"
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#include "base_cpu.hh"
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#include "exec_context.hh"
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#include "statistics.hh"
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#include "sim_stats.hh"
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class MemTest : public BaseCPU
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{
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public:
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MemTest(const std::string &name,
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MemInterface *_cache_interface,
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FunctionalMemory *main_mem,
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FunctionalMemory *check_mem,
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unsigned _memorySize,
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unsigned _percentReads,
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unsigned _percentUncacheable,
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unsigned _maxReads,
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unsigned _progressInterval,
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Addr _traceAddr);
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// register statistics
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virtual void regStats();
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// main simulation loop (one cycle)
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void tick();
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protected:
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class TickEvent : public Event
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{
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private:
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MemTest *cpu;
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public:
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TickEvent(MemTest *c)
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: Event(&mainEventQueue, 100), cpu(c) {}
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void process() {cpu->tick();}
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virtual const char *description() { return "tick event"; }
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};
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TickEvent tickEvent;
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MemInterface *cacheInterface;
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FunctionalMemory *mainMem;
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FunctionalMemory *checkMem;
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ExecContext *xc;
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unsigned size; // size of testing memory region
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unsigned percentReads; // target percentage of read accesses
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unsigned percentUncacheable;
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Tick maxReads; // max # of reads to perform (then quit)
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unsigned blockSize;
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Addr blockAddrMask;
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Addr blockAddr(Addr addr)
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{
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return (addr & ~blockAddrMask);
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}
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Addr traceBlockAddr;
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Addr baseAddr1; // fix this to option
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Addr baseAddr2; // fix this to option
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Addr uncacheAddr;
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unsigned progressInterval; // frequency of progress reports
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Tick nextProgressMessage; // access # for next progress report
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Tick noResponseCycles;
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Statistics::Scalar<long long int> numReads;
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Statistics::Scalar<long long int> numWrites;
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Statistics::Scalar<long long int> numCopies;
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// called by MemCompleteEvent::process()
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void completeRequest(MemReqPtr req, uint8_t *data);
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friend class MemCompleteEvent;
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};
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class MemCompleteEvent : public Event
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{
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MemReqPtr req;
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uint8_t *data;
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MemTest *tester;
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public:
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MemCompleteEvent(MemReqPtr _req, uint8_t *_data, MemTest *_tester)
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: Event(&mainEventQueue),
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req(_req), data(_data), tester(_tester)
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{
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}
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void process();
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virtual const char *description();
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};
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#endif // __MEMTEST_HH__
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