756 lines
24 KiB
C++
756 lines
24 KiB
C++
/*
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* Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include <cstring>
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#include "config/full_system.hh"
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#include "arch/x86/faults.hh"
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#include "arch/x86/insts/microldstop.hh"
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#include "arch/x86/miscregs.hh"
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#include "arch/x86/pagetable.hh"
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#include "arch/x86/tlb.hh"
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#include "arch/x86/x86_traits.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/base.hh"
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#include "mem/packet_access.hh"
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#include "mem/request.hh"
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#if FULL_SYSTEM
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#include "arch/x86/pagetable_walker.hh"
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#else
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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#endif
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namespace X86ISA {
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TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
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{
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tlb = new TlbEntry[size];
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std::memset(tlb, 0, sizeof(TlbEntry) * size);
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for (int x = 0; x < size; x++)
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freeList.push_back(&tlb[x]);
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#if FULL_SYSTEM
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walker = p->walker;
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walker->setTLB(this);
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#endif
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}
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TlbEntry *
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TLB::insert(Addr vpn, TlbEntry &entry)
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{
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//TODO Deal with conflicting entries
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TlbEntry *newEntry = NULL;
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if (!freeList.empty()) {
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newEntry = freeList.front();
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freeList.pop_front();
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} else {
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newEntry = entryList.back();
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entryList.pop_back();
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}
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*newEntry = entry;
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newEntry->vaddr = vpn;
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entryList.push_front(newEntry);
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return newEntry;
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}
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TLB::EntryList::iterator
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TLB::lookupIt(Addr va, bool update_lru)
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{
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//TODO make this smarter at some point
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EntryList::iterator entry;
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for (entry = entryList.begin(); entry != entryList.end(); entry++) {
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if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
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DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
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"with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
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if (update_lru) {
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entryList.push_front(*entry);
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entryList.erase(entry);
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entry = entryList.begin();
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}
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break;
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}
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}
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return entry;
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}
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TlbEntry *
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TLB::lookup(Addr va, bool update_lru)
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{
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EntryList::iterator entry = lookupIt(va, update_lru);
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if (entry == entryList.end())
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return NULL;
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else
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return *entry;
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}
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void
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TLB::invalidateAll()
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{
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DPRINTF(TLB, "Invalidating all entries.\n");
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while (!entryList.empty()) {
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TlbEntry *entry = entryList.front();
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entryList.pop_front();
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freeList.push_back(entry);
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}
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}
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void
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TLB::setConfigAddress(uint32_t addr)
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{
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configAddress = addr;
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}
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void
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TLB::invalidateNonGlobal()
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{
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DPRINTF(TLB, "Invalidating all non global entries.\n");
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EntryList::iterator entryIt;
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for (entryIt = entryList.begin(); entryIt != entryList.end();) {
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if (!(*entryIt)->global) {
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freeList.push_back(*entryIt);
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entryList.erase(entryIt++);
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} else {
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entryIt++;
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}
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}
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}
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void
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TLB::demapPage(Addr va, uint64_t asn)
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{
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EntryList::iterator entry = lookupIt(va, false);
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if (entry != entryList.end()) {
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freeList.push_back(*entry);
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entryList.erase(entry);
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}
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}
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Fault
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TLB::translateInt(RequestPtr req, ThreadContext *tc)
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{
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DPRINTF(TLB, "Addresses references internal memory.\n");
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Addr vaddr = req->getVaddr();
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Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
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if (prefix == IntAddrPrefixCPUID) {
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panic("CPUID memory space not yet implemented!\n");
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} else if (prefix == IntAddrPrefixMSR) {
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vaddr = vaddr >> 3;
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req->setFlags(Request::MMAPED_IPR);
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Addr regNum = 0;
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switch (vaddr & ~IntAddrPrefixMask) {
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case 0x10:
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regNum = MISCREG_TSC;
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break;
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case 0x1B:
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regNum = MISCREG_APIC_BASE;
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break;
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case 0xFE:
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regNum = MISCREG_MTRRCAP;
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break;
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case 0x174:
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regNum = MISCREG_SYSENTER_CS;
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break;
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case 0x175:
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regNum = MISCREG_SYSENTER_ESP;
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break;
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case 0x176:
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regNum = MISCREG_SYSENTER_EIP;
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break;
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case 0x179:
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regNum = MISCREG_MCG_CAP;
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break;
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case 0x17A:
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regNum = MISCREG_MCG_STATUS;
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break;
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case 0x17B:
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regNum = MISCREG_MCG_CTL;
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break;
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case 0x1D9:
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regNum = MISCREG_DEBUG_CTL_MSR;
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break;
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case 0x1DB:
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regNum = MISCREG_LAST_BRANCH_FROM_IP;
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break;
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case 0x1DC:
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regNum = MISCREG_LAST_BRANCH_TO_IP;
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break;
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case 0x1DD:
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regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
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break;
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case 0x1DE:
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regNum = MISCREG_LAST_EXCEPTION_TO_IP;
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break;
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case 0x200:
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regNum = MISCREG_MTRR_PHYS_BASE_0;
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break;
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case 0x201:
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regNum = MISCREG_MTRR_PHYS_MASK_0;
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break;
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case 0x202:
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regNum = MISCREG_MTRR_PHYS_BASE_1;
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break;
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case 0x203:
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regNum = MISCREG_MTRR_PHYS_MASK_1;
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break;
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case 0x204:
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regNum = MISCREG_MTRR_PHYS_BASE_2;
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break;
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case 0x205:
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regNum = MISCREG_MTRR_PHYS_MASK_2;
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break;
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case 0x206:
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regNum = MISCREG_MTRR_PHYS_BASE_3;
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break;
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case 0x207:
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regNum = MISCREG_MTRR_PHYS_MASK_3;
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break;
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case 0x208:
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regNum = MISCREG_MTRR_PHYS_BASE_4;
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break;
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case 0x209:
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regNum = MISCREG_MTRR_PHYS_MASK_4;
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break;
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case 0x20A:
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regNum = MISCREG_MTRR_PHYS_BASE_5;
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break;
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case 0x20B:
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regNum = MISCREG_MTRR_PHYS_MASK_5;
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break;
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case 0x20C:
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regNum = MISCREG_MTRR_PHYS_BASE_6;
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break;
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case 0x20D:
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regNum = MISCREG_MTRR_PHYS_MASK_6;
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break;
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case 0x20E:
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regNum = MISCREG_MTRR_PHYS_BASE_7;
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break;
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case 0x20F:
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regNum = MISCREG_MTRR_PHYS_MASK_7;
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break;
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case 0x250:
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regNum = MISCREG_MTRR_FIX_64K_00000;
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break;
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case 0x258:
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regNum = MISCREG_MTRR_FIX_16K_80000;
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break;
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case 0x259:
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regNum = MISCREG_MTRR_FIX_16K_A0000;
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break;
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case 0x268:
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regNum = MISCREG_MTRR_FIX_4K_C0000;
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break;
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case 0x269:
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regNum = MISCREG_MTRR_FIX_4K_C8000;
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break;
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case 0x26A:
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regNum = MISCREG_MTRR_FIX_4K_D0000;
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break;
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case 0x26B:
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regNum = MISCREG_MTRR_FIX_4K_D8000;
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break;
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case 0x26C:
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regNum = MISCREG_MTRR_FIX_4K_E0000;
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break;
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case 0x26D:
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regNum = MISCREG_MTRR_FIX_4K_E8000;
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break;
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case 0x26E:
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regNum = MISCREG_MTRR_FIX_4K_F0000;
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break;
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case 0x26F:
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regNum = MISCREG_MTRR_FIX_4K_F8000;
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break;
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case 0x277:
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regNum = MISCREG_PAT;
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break;
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case 0x2FF:
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regNum = MISCREG_DEF_TYPE;
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break;
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case 0x400:
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regNum = MISCREG_MC0_CTL;
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break;
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case 0x404:
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regNum = MISCREG_MC1_CTL;
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break;
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case 0x408:
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regNum = MISCREG_MC2_CTL;
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break;
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case 0x40C:
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regNum = MISCREG_MC3_CTL;
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break;
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case 0x410:
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regNum = MISCREG_MC4_CTL;
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break;
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case 0x414:
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regNum = MISCREG_MC5_CTL;
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break;
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case 0x418:
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regNum = MISCREG_MC6_CTL;
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break;
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case 0x41C:
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regNum = MISCREG_MC7_CTL;
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break;
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case 0x401:
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regNum = MISCREG_MC0_STATUS;
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break;
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case 0x405:
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regNum = MISCREG_MC1_STATUS;
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break;
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case 0x409:
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regNum = MISCREG_MC2_STATUS;
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break;
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case 0x40D:
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regNum = MISCREG_MC3_STATUS;
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break;
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case 0x411:
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regNum = MISCREG_MC4_STATUS;
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break;
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case 0x415:
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regNum = MISCREG_MC5_STATUS;
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break;
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case 0x419:
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regNum = MISCREG_MC6_STATUS;
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break;
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case 0x41D:
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regNum = MISCREG_MC7_STATUS;
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break;
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case 0x402:
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regNum = MISCREG_MC0_ADDR;
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break;
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case 0x406:
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regNum = MISCREG_MC1_ADDR;
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break;
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case 0x40A:
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regNum = MISCREG_MC2_ADDR;
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break;
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case 0x40E:
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regNum = MISCREG_MC3_ADDR;
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break;
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case 0x412:
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regNum = MISCREG_MC4_ADDR;
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break;
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case 0x416:
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regNum = MISCREG_MC5_ADDR;
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break;
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case 0x41A:
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regNum = MISCREG_MC6_ADDR;
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break;
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case 0x41E:
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regNum = MISCREG_MC7_ADDR;
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break;
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case 0x403:
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regNum = MISCREG_MC0_MISC;
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break;
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case 0x407:
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regNum = MISCREG_MC1_MISC;
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break;
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case 0x40B:
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regNum = MISCREG_MC2_MISC;
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break;
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case 0x40F:
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regNum = MISCREG_MC3_MISC;
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break;
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case 0x413:
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regNum = MISCREG_MC4_MISC;
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break;
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case 0x417:
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regNum = MISCREG_MC5_MISC;
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break;
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case 0x41B:
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regNum = MISCREG_MC6_MISC;
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break;
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case 0x41F:
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regNum = MISCREG_MC7_MISC;
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break;
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case 0xC0000080:
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regNum = MISCREG_EFER;
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break;
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case 0xC0000081:
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regNum = MISCREG_STAR;
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break;
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case 0xC0000082:
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regNum = MISCREG_LSTAR;
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break;
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case 0xC0000083:
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regNum = MISCREG_CSTAR;
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break;
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case 0xC0000084:
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regNum = MISCREG_SF_MASK;
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break;
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case 0xC0000100:
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regNum = MISCREG_FS_BASE;
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break;
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case 0xC0000101:
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regNum = MISCREG_GS_BASE;
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break;
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case 0xC0000102:
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regNum = MISCREG_KERNEL_GS_BASE;
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break;
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case 0xC0000103:
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regNum = MISCREG_TSC_AUX;
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break;
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case 0xC0010000:
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regNum = MISCREG_PERF_EVT_SEL0;
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break;
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case 0xC0010001:
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regNum = MISCREG_PERF_EVT_SEL1;
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break;
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case 0xC0010002:
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regNum = MISCREG_PERF_EVT_SEL2;
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break;
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case 0xC0010003:
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regNum = MISCREG_PERF_EVT_SEL3;
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break;
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case 0xC0010004:
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regNum = MISCREG_PERF_EVT_CTR0;
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break;
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case 0xC0010005:
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regNum = MISCREG_PERF_EVT_CTR1;
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break;
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case 0xC0010006:
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regNum = MISCREG_PERF_EVT_CTR2;
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break;
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case 0xC0010007:
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regNum = MISCREG_PERF_EVT_CTR3;
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break;
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case 0xC0010010:
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regNum = MISCREG_SYSCFG;
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break;
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case 0xC0010016:
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regNum = MISCREG_IORR_BASE0;
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break;
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case 0xC0010017:
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regNum = MISCREG_IORR_BASE1;
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break;
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case 0xC0010018:
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regNum = MISCREG_IORR_MASK0;
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break;
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case 0xC0010019:
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regNum = MISCREG_IORR_MASK1;
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break;
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case 0xC001001A:
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regNum = MISCREG_TOP_MEM;
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break;
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case 0xC001001D:
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regNum = MISCREG_TOP_MEM2;
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break;
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case 0xC0010114:
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regNum = MISCREG_VM_CR;
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break;
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case 0xC0010115:
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regNum = MISCREG_IGNNE;
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break;
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case 0xC0010116:
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regNum = MISCREG_SMM_CTL;
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break;
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case 0xC0010117:
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regNum = MISCREG_VM_HSAVE_PA;
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break;
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default:
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return new GeneralProtection(0);
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}
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//The index is multiplied by the size of a MiscReg so that
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//any memory dependence calculations will not see these as
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//overlapping.
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req->setPaddr(regNum * sizeof(MiscReg));
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return NoFault;
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} else if (prefix == IntAddrPrefixIO) {
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// TODO If CPL > IOPL or in virtual mode, check the I/O permission
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// bitmap in the TSS.
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Addr IOPort = vaddr & ~IntAddrPrefixMask;
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// Make sure the address fits in the expected 16 bit IO address
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// space.
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assert(!(IOPort & ~0xFFFF));
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if (IOPort == 0xCF8 && req->getSize() == 4) {
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req->setFlags(Request::MMAPED_IPR);
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req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
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} else if ((IOPort & ~mask(2)) == 0xCFC) {
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Addr configAddress =
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tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
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if (bits(configAddress, 31, 31)) {
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req->setPaddr(PhysAddrPrefixPciConfig |
|
|
mbits(configAddress, 30, 2) |
|
|
(IOPort & mask(2)));
|
|
}
|
|
} else {
|
|
req->setPaddr(PhysAddrPrefixIO | IOPort);
|
|
}
|
|
return NoFault;
|
|
} else {
|
|
panic("Access to unrecognized internal address space %#x.\n",
|
|
prefix);
|
|
}
|
|
}
|
|
|
|
Fault
|
|
TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
|
|
Mode mode, bool &delayedResponse, bool timing)
|
|
{
|
|
uint32_t flags = req->getFlags();
|
|
int seg = flags & SegmentFlagMask;
|
|
bool storeCheck = flags & (StoreCheck << FlagShift);
|
|
|
|
// If this is true, we're dealing with a request to a non-memory address
|
|
// space.
|
|
if (seg == SEGMENT_REG_MS) {
|
|
return translateInt(req, tc);
|
|
}
|
|
|
|
delayedResponse = false;
|
|
Addr vaddr = req->getVaddr();
|
|
DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
|
|
|
|
HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
|
|
|
|
// If protected mode has been enabled...
|
|
if (m5Reg.prot) {
|
|
DPRINTF(TLB, "In protected mode.\n");
|
|
// If we're not in 64-bit mode, do protection/limit checks
|
|
if (m5Reg.mode != LongMode) {
|
|
DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
|
|
// Check for a NULL segment selector.
|
|
if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
|
|
seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
|
|
&& !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
|
|
return new GeneralProtection(0);
|
|
bool expandDown = false;
|
|
SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
|
|
if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
|
|
if (!attr.writable && (mode == Write || storeCheck))
|
|
return new GeneralProtection(0);
|
|
if (!attr.readable && mode == Read)
|
|
return new GeneralProtection(0);
|
|
expandDown = attr.expandDown;
|
|
|
|
}
|
|
Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
|
|
Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
|
|
// This assumes we're not in 64 bit mode. If we were, the default
|
|
// address size is 64 bits, overridable to 32.
|
|
int size = 32;
|
|
bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
|
|
SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
|
|
if ((csAttr.defaultSize && sizeOverride) ||
|
|
(!csAttr.defaultSize && !sizeOverride))
|
|
size = 16;
|
|
Addr offset = bits(vaddr - base, size-1, 0);
|
|
Addr endOffset = offset + req->getSize() - 1;
|
|
if (expandDown) {
|
|
DPRINTF(TLB, "Checking an expand down segment.\n");
|
|
warn_once("Expand down segments are untested.\n");
|
|
if (offset <= limit || endOffset <= limit)
|
|
return new GeneralProtection(0);
|
|
} else {
|
|
if (offset > limit || endOffset > limit)
|
|
return new GeneralProtection(0);
|
|
}
|
|
}
|
|
// If paging is enabled, do the translation.
|
|
if (m5Reg.paging) {
|
|
DPRINTF(TLB, "Paging enabled.\n");
|
|
// The vaddr already has the segment base applied.
|
|
TlbEntry *entry = lookup(vaddr);
|
|
if (!entry) {
|
|
#if FULL_SYSTEM
|
|
Fault fault = walker->start(tc, translation, req, mode);
|
|
if (timing || fault != NoFault) {
|
|
// This gets ignored in atomic mode.
|
|
delayedResponse = true;
|
|
return fault;
|
|
}
|
|
entry = lookup(vaddr);
|
|
assert(entry);
|
|
#else
|
|
DPRINTF(TLB, "Handling a TLB miss for "
|
|
"address %#x at pc %#x.\n",
|
|
vaddr, tc->readPC());
|
|
|
|
Process *p = tc->getProcessPtr();
|
|
TlbEntry newEntry;
|
|
bool success = p->pTable->lookup(vaddr, newEntry);
|
|
if (!success && mode != Execute) {
|
|
p->checkAndAllocNextPage(vaddr);
|
|
success = p->pTable->lookup(vaddr, newEntry);
|
|
}
|
|
if (!success) {
|
|
if (req->isPrefetch()) {
|
|
return new PageFault(vaddr, true, mode, true, false);
|
|
} else {
|
|
const char *modeStr = "";
|
|
if (mode == Execute)
|
|
modeStr = "execute";
|
|
else if (mode == Read)
|
|
modeStr = "read";
|
|
else if (mode == Write)
|
|
modeStr = "write";
|
|
else
|
|
modeStr = "?";
|
|
panic("Tried to %s unmapped address %#x.\n",
|
|
modeStr, vaddr);
|
|
}
|
|
} else {
|
|
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
|
|
DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
|
|
newEntry.pageStart());
|
|
entry = insert(alignedVaddr, newEntry);
|
|
}
|
|
DPRINTF(TLB, "Miss was serviced.\n");
|
|
#endif
|
|
}
|
|
// Do paging protection checks.
|
|
bool inUser = (m5Reg.cpl == 3 &&
|
|
!(flags & (CPL0FlagBit << FlagShift)));
|
|
if ((inUser && !entry->user) ||
|
|
(mode == Write && !entry->writable)) {
|
|
// The page must have been present to get into the TLB in
|
|
// the first place. We'll assume the reserved bits are
|
|
// fine even though we're not checking them.
|
|
return new PageFault(vaddr, true, mode, inUser, false);
|
|
}
|
|
if (storeCheck && !entry->writable) {
|
|
// This would fault if this were a write, so return a page
|
|
// fault that reflects that happening.
|
|
return new PageFault(vaddr, true, Write, inUser, false);
|
|
}
|
|
|
|
|
|
DPRINTF(TLB, "Entry found with paddr %#x, "
|
|
"doing protection checks.\n", entry->paddr);
|
|
Addr paddr = entry->paddr | (vaddr & (entry->size-1));
|
|
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
|
|
req->setPaddr(paddr);
|
|
} else {
|
|
//Use the address which already has segmentation applied.
|
|
DPRINTF(TLB, "Paging disabled.\n");
|
|
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
|
|
req->setPaddr(vaddr);
|
|
}
|
|
} else {
|
|
// Real mode
|
|
DPRINTF(TLB, "In real mode.\n");
|
|
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
|
|
req->setPaddr(vaddr);
|
|
}
|
|
// Check for an access to the local APIC
|
|
#if FULL_SYSTEM
|
|
LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
|
|
Addr baseAddr = localApicBase.base * PageBytes;
|
|
Addr paddr = req->getPaddr();
|
|
if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
|
|
// The Intel developer's manuals say the below restrictions apply,
|
|
// but the linux kernel, because of a compiler optimization, breaks
|
|
// them.
|
|
/*
|
|
// Check alignment
|
|
if (paddr & ((32/8) - 1))
|
|
return new GeneralProtection(0);
|
|
// Check access size
|
|
if (req->getSize() != (32/8))
|
|
return new GeneralProtection(0);
|
|
*/
|
|
// Force the access to be uncacheable.
|
|
req->setFlags(Request::UNCACHEABLE);
|
|
req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
|
|
}
|
|
#endif
|
|
return NoFault;
|
|
};
|
|
|
|
Fault
|
|
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
|
|
{
|
|
bool delayedResponse;
|
|
return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
|
|
}
|
|
|
|
void
|
|
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
|
|
Translation *translation, Mode mode)
|
|
{
|
|
bool delayedResponse;
|
|
assert(translation);
|
|
Fault fault =
|
|
TLB::translate(req, tc, translation, mode, delayedResponse, true);
|
|
if (!delayedResponse)
|
|
translation->finish(fault, req, tc, mode);
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
Tick
|
|
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
|
|
{
|
|
return tc->getCpuPtr()->ticks(1);
|
|
}
|
|
|
|
Tick
|
|
TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
|
|
{
|
|
return tc->getCpuPtr()->ticks(1);
|
|
}
|
|
|
|
#endif
|
|
|
|
void
|
|
TLB::serialize(std::ostream &os)
|
|
{
|
|
}
|
|
|
|
void
|
|
TLB::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
}
|
|
|
|
/* end namespace X86ISA */ }
|
|
|
|
X86ISA::TLB *
|
|
X86TLBParams::create()
|
|
{
|
|
return new X86ISA::TLB(this);
|
|
}
|