c240d4af84
--HG-- rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini => tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out => tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.out => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pin => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl1 => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.pl2 => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sav => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.sv2 => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/smred.twf => tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr rename : tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.out => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pin => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl1 => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.pl2 => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sav => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.sv2 => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/smred.twf => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr rename : tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini => tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out => tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.out => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pin => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl1 => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.pl2 => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sav => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.sv2 => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/smred.twf => tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr rename : tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout extra : convert_revision : 55f9327662e0902925ca14b3260a86f7d211d445
201 lines
3.3 KiB
Text
201 lines
3.3 KiB
Text
[root]
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type=Root
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clock=1000000000000
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max_tick=0
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progress_interval=0
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output_file=cout
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[system.physmem]
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type=PhysicalMemory
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file=
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range=[0,134217727]
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latency=1
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zero=false
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[system]
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type=System
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physmem=system.physmem
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mem_mode=atomic
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[system.membus]
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type=Bus
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bus_id=0
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clock=1000
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width=64
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responder_set=false
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[system.cpu.workload]
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type=LiveProcess
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cmd=twolf smred
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
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input=cin
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output=cout
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env=
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cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing
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system=system
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uid=100
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euid=100
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gid=100
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egid=100
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pid=100
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ppid=99
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[system.cpu]
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type=TimingSimpleCPU
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max_insts_any_thread=0
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max_insts_all_threads=0
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max_loads_any_thread=0
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max_loads_all_threads=0
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progress_interval=0
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system=system
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cpu_id=0
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workload=system.cpu.workload
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clock=1
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phase=0
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defer_registration=false
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// width not specified
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function_trace=false
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function_trace_start=0
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// simulate_stalls not specified
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[system.cpu.toL2Bus]
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type=Bus
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bus_id=0
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clock=1000
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width=64
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responder_set=false
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[system.cpu.icache]
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type=BaseCache
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size=131072
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assoc=2
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block_size=64
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latency=1
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mshrs=10
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tgts_per_mshr=5
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write_buffers=8
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prioritizeRequests=false
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protocol=null
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trace_addr=0
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hash_delay=1
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repl=null
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compressed_bus=false
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store_compressed=false
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adaptive_compression=false
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compression_latency=0
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block_size=64
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max_miss_count=0
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addr_range=[0,18446744073709551615]
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split=false
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split_size=0
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lifo=false
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two_queue=false
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prefetch_miss=false
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prefetch_access=false
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prefetcher_size=100
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prefetch_past_page=false
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prefetch_serial_squash=false
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prefetch_latency=10
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prefetch_degree=1
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prefetch_policy=none
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prefetch_cache_check_push=true
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prefetch_use_cpu_id=true
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prefetch_data_accesses_only=false
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hit_latency=1
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[system.cpu.dcache]
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type=BaseCache
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size=262144
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assoc=2
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block_size=64
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latency=1
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mshrs=10
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tgts_per_mshr=5
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write_buffers=8
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prioritizeRequests=false
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protocol=null
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trace_addr=0
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hash_delay=1
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repl=null
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compressed_bus=false
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store_compressed=false
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adaptive_compression=false
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compression_latency=0
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block_size=64
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max_miss_count=0
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addr_range=[0,18446744073709551615]
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split=false
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split_size=0
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lifo=false
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two_queue=false
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prefetch_miss=false
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prefetch_access=false
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prefetcher_size=100
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prefetch_past_page=false
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prefetch_serial_squash=false
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prefetch_latency=10
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prefetch_degree=1
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prefetch_policy=none
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prefetch_cache_check_push=true
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prefetch_use_cpu_id=true
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prefetch_data_accesses_only=false
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hit_latency=1
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[system.cpu.l2cache]
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type=BaseCache
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size=2097152
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assoc=2
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block_size=64
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latency=1
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mshrs=10
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tgts_per_mshr=5
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write_buffers=8
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prioritizeRequests=false
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protocol=null
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trace_addr=0
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hash_delay=1
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repl=null
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compressed_bus=false
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store_compressed=false
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adaptive_compression=false
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compression_latency=0
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block_size=64
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max_miss_count=0
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addr_range=[0,18446744073709551615]
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split=false
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split_size=0
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lifo=false
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two_queue=false
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prefetch_miss=false
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prefetch_access=false
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prefetcher_size=100
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prefetch_past_page=false
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prefetch_serial_squash=false
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prefetch_latency=10
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prefetch_degree=1
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prefetch_policy=none
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prefetch_cache_check_push=true
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prefetch_use_cpu_id=true
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prefetch_data_accesses_only=false
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hit_latency=1
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[stats]
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descriptions=true
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project_name=test
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simulation_name=test
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simulation_sample=0
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text_file=m5stats.txt
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text_compat=true
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mysql_db=
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mysql_user=
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mysql_password=
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mysql_host=
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events_start=-1
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dump_reset=false
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dump_cycle=0
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dump_period=0
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ignore_events=
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[statsreset]
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reset_cycle=0
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