b331b02669
Rather tha constantly using ULL(1) << PcXBitShift define those directly. Additionally, add some helper functions to further clean up the code.
444 lines
15 KiB
C++
444 lines
15 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#include "arch/arm/isa.hh"
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#include "sim/faults.hh"
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namespace ArmISA
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{
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void
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ISA::clear()
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{
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SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
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memset(miscRegs, 0, sizeof(miscRegs));
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CPSR cpsr = 0;
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cpsr.mode = MODE_USER;
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miscRegs[MISCREG_CPSR] = cpsr;
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updateRegMap(cpsr);
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SCTLR sctlr = 0;
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sctlr.te = (bool)sctlr_rst.te;
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sctlr.nmfi = (bool)sctlr_rst.nmfi;
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sctlr.v = (bool)sctlr_rst.v;
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sctlr.u = 1;
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sctlr.xp = 1;
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sctlr.rao2 = 1;
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sctlr.rao3 = 1;
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sctlr.rao4 = 1;
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miscRegs[MISCREG_SCTLR] = sctlr;
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miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
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/* Start with an event in the mailbox */
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miscRegs[MISCREG_SEV_MAILBOX] = 1;
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/*
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* Implemented = '5' from "M5",
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* Variant = 0,
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*/
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miscRegs[MISCREG_MIDR] =
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(0x35 << 24) | // Implementor is '5' from "M5"
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(0 << 20) | // Variant
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(0xf << 16) | // Architecture from CPUID scheme
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(0xf00 << 4) | // Primary part number
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(0 << 0) | // Revision
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0;
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// Separate Instruction and Data TLBs.
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miscRegs[MISCREG_TLBTR] = 1;
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MVFR0 mvfr0 = 0;
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mvfr0.advSimdRegisters = 2;
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mvfr0.singlePrecision = 2;
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mvfr0.doublePrecision = 2;
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mvfr0.vfpExceptionTrapping = 0;
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mvfr0.divide = 1;
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mvfr0.squareRoot = 1;
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mvfr0.shortVectors = 1;
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mvfr0.roundingModes = 1;
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miscRegs[MISCREG_MVFR0] = mvfr0;
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MVFR1 mvfr1 = 0;
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mvfr1.flushToZero = 1;
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mvfr1.defaultNaN = 1;
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mvfr1.advSimdLoadStore = 1;
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mvfr1.advSimdInteger = 1;
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mvfr1.advSimdSinglePrecision = 1;
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mvfr1.advSimdHalfPrecision = 1;
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mvfr1.vfpHalfPrecision = 1;
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miscRegs[MISCREG_MVFR1] = mvfr1;
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miscRegs[MISCREG_MPIDR] = 0;
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// Reset values of PRRR and NMRR are implementation dependent
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miscRegs[MISCREG_PRRR] =
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(1 << 19) | // 19
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(0 << 18) | // 18
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(0 << 17) | // 17
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(1 << 16) | // 16
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(2 << 14) | // 15:14
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(0 << 12) | // 13:12
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(2 << 10) | // 11:10
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(2 << 8) | // 9:8
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(2 << 6) | // 7:6
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(2 << 4) | // 5:4
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(1 << 2) | // 3:2
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0; // 1:0
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miscRegs[MISCREG_NMRR] =
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(1 << 30) | // 31:30
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(0 << 26) | // 27:26
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(0 << 24) | // 25:24
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(3 << 22) | // 23:22
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(2 << 20) | // 21:20
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(0 << 18) | // 19:18
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(0 << 16) | // 17:16
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(1 << 14) | // 15:14
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(0 << 12) | // 13:12
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(2 << 10) | // 11:10
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(0 << 8) | // 9:8
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(3 << 6) | // 7:6
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(2 << 4) | // 5:4
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(0 << 2) | // 3:2
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0; // 1:0
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miscRegs[MISCREG_CPACR] = 0;
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miscRegs[MISCREG_FPSID] = 0x410430A0;
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//XXX We need to initialize the rest of the state.
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}
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MiscReg
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ISA::readMiscRegNoEffect(int misc_reg)
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{
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assert(misc_reg < NumMiscRegs);
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int flat_idx;
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if (misc_reg == MISCREG_SPSR)
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flat_idx = flattenMiscIndex(misc_reg);
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else
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flat_idx = misc_reg;
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MiscReg val = miscRegs[flat_idx];
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DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
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misc_reg, flat_idx, val);
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return val;
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}
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MiscReg
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ISA::readMiscReg(int misc_reg, ThreadContext *tc)
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{
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if (misc_reg == MISCREG_CPSR) {
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CPSR cpsr = miscRegs[misc_reg];
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Addr pc = tc->readPC();
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if (pc & (ULL(1) << PcJBitShift))
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cpsr.j = 1;
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else
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cpsr.j = 0;
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if (isThumb(pc))
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cpsr.t = 1;
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else
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cpsr.t = 0;
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return cpsr;
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}
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if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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panic("Unimplemented CP15 register %s read.\n",
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miscRegName[misc_reg]);
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}
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switch (misc_reg) {
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case MISCREG_CLIDR:
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warn("The clidr register always reports 0 caches.\n");
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break;
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case MISCREG_CCSIDR:
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warn("The ccsidr register isn't implemented and "
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"always reads as 0.\n");
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break;
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case MISCREG_ID_PFR0:
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warn("Returning thumbEE disabled for now since we don't support CP14"
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"config registers and jumping to ThumbEE vectors\n");
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return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
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case MISCREG_ID_MMFR0:
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return 0x03; //VMSAz7
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case MISCREG_CTR:
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return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
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case MISCREG_ACTLR:
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warn("Not doing anything for miscreg ACTLR\n");
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break;
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case MISCREG_PMCR:
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case MISCREG_PMCCNTR:
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case MISCREG_PMSELR:
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warn("Not doing anyhting for read to miscreg %s\n",
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miscRegName[misc_reg]);
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break;
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}
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return readMiscRegNoEffect(misc_reg);
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}
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void
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ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{
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assert(misc_reg < NumMiscRegs);
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int flat_idx;
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if (misc_reg == MISCREG_SPSR)
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flat_idx = flattenMiscIndex(misc_reg);
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else
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flat_idx = misc_reg;
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miscRegs[flat_idx] = val;
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DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
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flat_idx, val);
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}
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void
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ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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{
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MiscReg newVal = val;
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if (misc_reg == MISCREG_CPSR) {
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updateRegMap(val);
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CPSR cpsr = val;
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DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
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miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
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Addr npc = tc->readNextPC() & ~PcModeMask;
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if (cpsr.j)
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npc = npc | PcJBit;
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if (cpsr.t)
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npc = npc | PcTBit;
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tc->setNextPC(npc);
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} else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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panic("Unimplemented CP15 register %s wrote with %#x.\n",
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miscRegName[misc_reg], val);
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} else {
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switch (misc_reg) {
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case MISCREG_ITSTATE:
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{
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ITSTATE itstate = newVal;
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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cpsr.it1 = itstate.bottom2;
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cpsr.it2 = itstate.top6;
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miscRegs[MISCREG_CPSR] = cpsr;
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DPRINTF(MiscRegs,
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"Updating ITSTATE -> %#x in CPSR -> %#x.\n",
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(uint8_t)itstate, (uint32_t)cpsr);
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}
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break;
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case MISCREG_CPACR:
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{
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CPACR newCpacr = 0;
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CPACR valCpacr = val;
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newCpacr.cp10 = valCpacr.cp10;
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newCpacr.cp11 = valCpacr.cp11;
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//XXX d32dis isn't implemented. The manual says whether or not
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//it works is implementation defined.
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newCpacr.asedis = valCpacr.asedis;
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newVal = newCpacr;
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}
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break;
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case MISCREG_CSSELR:
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warn("The csselr register isn't implemented.\n");
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break;
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case MISCREG_FPSCR:
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{
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const uint32_t ones = (uint32_t)(-1);
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FPSCR fpscrMask = 0;
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fpscrMask.ioc = ones;
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fpscrMask.dzc = ones;
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fpscrMask.ofc = ones;
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fpscrMask.ufc = ones;
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fpscrMask.ixc = ones;
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fpscrMask.idc = ones;
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fpscrMask.len = ones;
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fpscrMask.stride = ones;
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fpscrMask.rMode = ones;
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fpscrMask.fz = ones;
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fpscrMask.dn = ones;
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fpscrMask.ahp = ones;
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fpscrMask.qc = ones;
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fpscrMask.v = ones;
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fpscrMask.c = ones;
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fpscrMask.z = ones;
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fpscrMask.n = ones;
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newVal = (newVal & (uint32_t)fpscrMask) |
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(miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
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}
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break;
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case MISCREG_FPEXC:
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{
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const uint32_t fpexcMask = 0x60000000;
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newVal = (newVal & fpexcMask) |
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(miscRegs[MISCREG_FPEXC] & ~fpexcMask);
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}
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break;
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case MISCREG_SCTLR:
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{
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DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
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SCTLR sctlr = miscRegs[MISCREG_SCTLR];
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SCTLR new_sctlr = newVal;
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new_sctlr.nmfi = (bool)sctlr.nmfi;
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miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
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return;
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}
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case MISCREG_TLBTR:
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case MISCREG_MVFR0:
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case MISCREG_MVFR1:
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case MISCREG_MPIDR:
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case MISCREG_FPSID:
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return;
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case MISCREG_TLBIALLIS:
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case MISCREG_TLBIALL:
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warn("Need to flush all TLBs in MP\n");
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tc->getITBPtr()->flushAll();
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tc->getDTBPtr()->flushAll();
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return;
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case MISCREG_ITLBIALL:
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tc->getITBPtr()->flushAll();
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return;
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case MISCREG_DTLBIALL:
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tc->getDTBPtr()->flushAll();
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return;
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case MISCREG_TLBIMVAIS:
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case MISCREG_TLBIMVA:
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warn("Need to flush all TLBs in MP\n");
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tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
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bits(newVal, 7,0));
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tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
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bits(newVal, 7,0));
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return;
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case MISCREG_TLBIASIDIS:
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case MISCREG_TLBIASID:
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warn("Need to flush all TLBs in MP\n");
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tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
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tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
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return;
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case MISCREG_TLBIMVAAIS:
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case MISCREG_TLBIMVAA:
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warn("Need to flush all TLBs in MP\n");
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tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
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tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
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return;
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case MISCREG_ITLBIMVA:
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tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
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bits(newVal, 7,0));
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return;
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case MISCREG_DTLBIMVA:
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tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
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bits(newVal, 7,0));
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return;
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case MISCREG_ITLBIASID:
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tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
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return;
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case MISCREG_DTLBIASID:
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tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
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return;
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case MISCREG_ACTLR:
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warn("Not doing anything for write of miscreg ACTLR\n");
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break;
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case MISCREG_PMCR:
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case MISCREG_PMCCNTR:
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case MISCREG_PMSELR:
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warn("Not doing anything for write to miscreg %s\n",
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miscRegName[misc_reg]);
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break;
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case MISCREG_V2PCWPR:
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case MISCREG_V2PCWPW:
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case MISCREG_V2PCWUR:
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case MISCREG_V2PCWUW:
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case MISCREG_V2POWPR:
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case MISCREG_V2POWPW:
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case MISCREG_V2POWUR:
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case MISCREG_V2POWUW:
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{
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RequestPtr req = new Request;
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unsigned flags;
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BaseTLB::Mode mode;
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Fault fault;
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switch(misc_reg) {
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case MISCREG_V2PCWPR:
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flags = TLB::MustBeOne;
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mode = BaseTLB::Read;
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break;
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case MISCREG_V2PCWPW:
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flags = TLB::MustBeOne;
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mode = BaseTLB::Write;
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break;
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case MISCREG_V2PCWUR:
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flags = TLB::MustBeOne | TLB::UserMode;
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mode = BaseTLB::Read;
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break;
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case MISCREG_V2PCWUW:
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flags = TLB::MustBeOne | TLB::UserMode;
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mode = BaseTLB::Write;
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break;
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default:
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panic("Security Extensions not implemented!");
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}
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req->setVirt(0, val, 1, flags, tc->readPC());
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fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
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if (fault == NoFault) {
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miscRegs[MISCREG_PAR] =
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(req->getPaddr() & 0xfffff000) |
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(tc->getDTBPtr()->getAttr() );
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DPRINTF(MiscRegs,
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"MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
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val, miscRegs[MISCREG_PAR]);
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}
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else {
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// Set fault bit and FSR
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FSR fsr = miscRegs[MISCREG_DFSR];
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miscRegs[MISCREG_PAR] =
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(fsr.ext << 6) |
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(fsr.fsHigh << 5) |
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(fsr.fsLow << 1) |
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0x1; // F bit
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}
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return;
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}
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}
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}
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setMiscRegNoEffect(misc_reg, newVal);
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}
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}
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