cpu/base_cpu.cc: cpu/base_cpu.hh: Convert the CPU stuff to use a params struct cpu/memtest/memtest.cc: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. Don't have any default parameters. cpu/memtest/memtest.hh: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. cpu/simple_cpu/simple_cpu.cc: Convert to use a params struct. remove default parameters cpu/simple_cpu/simple_cpu.hh: convert to use a params struct cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: this isn't really a cpu. don't derive from BaseCPU objects/MemTest.mpy: we only need one max_loads parameter sim/main.cc: Don't check for the number of CPUs since we may be doing something else going on. If we don't have anything to simulate, the simulator will exit anyway. --HG-- extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5
179 lines
5.4 KiB
C++
179 lines
5.4 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Declaration of a memory trace CPU object. Uses a memory trace to drive the
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* provided memory hierarchy.
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*/
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#include <algorithm> // For min
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#include "cpu/trace/trace_cpu.hh"
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#include "cpu/trace/reader/mem_trace_reader.hh"
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#include "mem/base_mem.hh" // For PARAM constructor
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#include "mem/mem_interface.hh"
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#include "sim/builder.hh"
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#include "sim/sim_events.hh"
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using namespace std;
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TraceCPU::TraceCPU(const string &name,
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MemInterface *icache_interface,
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MemInterface *dcache_interface,
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MemTraceReader *data_trace)
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: SimObject(name), icacheInterface(icache_interface),
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dcacheInterface(dcache_interface),
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dataTrace(data_trace), outstandingRequests(0), tickEvent(this)
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{
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assert(dcacheInterface);
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nextCycle = dataTrace->getNextReq(nextReq);
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tickEvent.schedule(0);
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}
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void
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TraceCPU::tick()
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{
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assert(outstandingRequests >= 0);
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assert(outstandingRequests < 1000);
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int instReqs = 0;
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int dataReqs = 0;
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while (nextReq && curTick >= nextCycle) {
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assert(nextReq->thread_num < 4 && "Not enough threads");
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if (nextReq->isInstRead() && icacheInterface) {
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if (icacheInterface->isBlocked())
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break;
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nextReq->time = curTick;
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if (nextReq->cmd == Squash) {
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icacheInterface->squash(nextReq->asid);
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} else {
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++instReqs;
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if (icacheInterface->doEvents()) {
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nextReq->completionEvent =
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new TraceCompleteEvent(nextReq, this);
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icacheInterface->access(nextReq);
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} else {
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icacheInterface->access(nextReq);
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completeRequest(nextReq);
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}
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}
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} else {
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if (dcacheInterface->isBlocked())
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break;
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++dataReqs;
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nextReq->time = curTick;
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if (dcacheInterface->doEvents()) {
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nextReq->completionEvent =
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new TraceCompleteEvent(nextReq, this);
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dcacheInterface->access(nextReq);
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} else {
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dcacheInterface->access(nextReq);
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completeRequest(nextReq);
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}
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}
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nextCycle = dataTrace->getNextReq(nextReq);
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}
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if (!nextReq) {
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// No more requests to send. Finish trailing events and exit.
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if (mainEventQueue.empty()) {
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new SimExitEvent("Finshed Memory Trace");
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} else {
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tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
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}
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} else {
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tickEvent.schedule(max(curTick + 1, nextCycle));
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}
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}
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void
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TraceCPU::completeRequest(MemReqPtr& req)
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{
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}
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void
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TraceCompleteEvent::process()
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{
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tester->completeRequest(req);
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}
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const char *
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TraceCompleteEvent::description()
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{
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return "trace access complete";
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}
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TraceCPU::TickEvent::TickEvent(TraceCPU *c)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
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{
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}
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void
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TraceCPU::TickEvent::process()
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{
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cpu->tick();
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}
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const char *
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TraceCPU::TickEvent::description()
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{
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return "TraceCPU tick event";
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
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SimObjectParam<BaseMem *> icache;
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SimObjectParam<BaseMem *> dcache;
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SimObjectParam<MemTraceReader *> data_trace;
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END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
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BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
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INIT_PARAM_DFLT(icache, "instruction cache", NULL),
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INIT_PARAM_DFLT(dcache, "data cache", NULL),
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INIT_PARAM_DFLT(data_trace, "data trace", NULL)
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END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
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CREATE_SIM_OBJECT(TraceCPU)
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{
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return new TraceCPU(getInstanceName(),
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(icache) ? icache->getInterface() : NULL,
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(dcache) ? dcache->getInterface() : NULL,
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data_trace);
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}
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REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
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