cpu/base_cpu.cc: cpu/base_cpu.hh: Convert the CPU stuff to use a params struct cpu/memtest/memtest.cc: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. Don't have any default parameters. cpu/memtest/memtest.hh: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. cpu/simple_cpu/simple_cpu.cc: Convert to use a params struct. remove default parameters cpu/simple_cpu/simple_cpu.hh: convert to use a params struct cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: this isn't really a cpu. don't derive from BaseCPU objects/MemTest.mpy: we only need one max_loads parameter sim/main.cc: Don't check for the number of CPUs since we may be doing something else going on. If we don't have anything to simulate, the simulator will exit anyway. --HG-- extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5
223 lines
6.1 KiB
C++
223 lines
6.1 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Declaration of a memory trace CPU object for optimal caches. Uses a memory
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* trace to access a fully associative cache with optimal replacement.
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*/
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#ifndef __CPU_TRACE_OPT_CPU_HH__
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#define __CPU_TRACE_OPT_CPU_HH__
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#include <vector>
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#include "mem/mem_req.hh" // for MemReqPtr
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#include "sim/eventq.hh" // for Event
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#include "sim/sim_object.hh"
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// Forward Declaration
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class MemTraceReader;
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/**
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* A CPU object to simulate a fully-associative cache with optimal replacement.
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*/
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class OptCPU : public SimObject
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{
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private:
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typedef int RefIndex;
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typedef std::vector<RefIndex> L3Table;
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typedef std::vector<L3Table> L2Table;
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typedef std::vector<L2Table> L1Table;
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/**
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* Event to call OptCPU::tick
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*/
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class TickEvent : public Event
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{
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private:
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/** The associated CPU */
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OptCPU *cpu;
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public:
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/**
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* Construct this event;
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*/
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TickEvent(OptCPU *c);
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/**
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* Call the tick function.
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*/
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void process();
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/**
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* Return a string description of this event.
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*/
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const char *description();
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};
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TickEvent tickEvent;
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class RefInfo
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{
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public:
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RefIndex nextRefTime;
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Addr addr;
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};
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/** Reference Information, per set. */
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std::vector<std::vector<RefInfo> > refInfo;
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/** Lookup table to track blocks in the cache heap */
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L1Table lookupTable;
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/**
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* Return the correct value in the lookup table.
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*/
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RefIndex lookupValue(Addr addr)
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{
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int l1_index = (addr >> 32) & 0x0f;
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int l2_index = (addr >> 16) & 0xffff;
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int l3_index = addr & 0xffff;
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assert(l1_index == addr >> 32);
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return lookupTable[l1_index][l2_index][l3_index];
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}
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/**
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* Set the value in the lookup table.
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*/
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void setValue(Addr addr, RefIndex index)
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{
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int l1_index = (addr >> 32) & 0x0f;
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int l2_index = (addr >> 16) & 0xffff;
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int l3_index = addr & 0xffff;
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assert(l1_index == addr >> 32);
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lookupTable[l1_index][l2_index][l3_index]=index;
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}
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/**
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* Initialize the lookup table to the given value.
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*/
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void initTable(Addr addr, RefIndex index);
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void heapSwap(int set, int a, int b) {
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RefIndex tmp = cacheHeap[a];
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cacheHeap[a] = cacheHeap[b];
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cacheHeap[b] = tmp;
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setValue(refInfo[set][cacheHeap[a]].addr, a);
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setValue(refInfo[set][cacheHeap[b]].addr, b);
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}
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int heapLeft(int index) { return index + index + 1; }
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int heapRight(int index) { return index + index + 2; }
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int heapParent(int index) { return (index - 1) >> 1; }
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RefIndex heapRank(int set, int index) {
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return refInfo[set][cacheHeap[index]].nextRefTime;
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}
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void heapify(int set, int start){
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int left = heapLeft(start);
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int right = heapRight(start);
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int max = start;
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if (left < assoc && heapRank(set, left) > heapRank(set, start)) {
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max = left;
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}
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if (right < assoc && heapRank(set, right) > heapRank(set, max)) {
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max = right;
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}
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if (max != start) {
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heapSwap(set, start, max);
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heapify(set, max);
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}
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}
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void verifyHeap(int set, int start) {
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int left = heapLeft(start);
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int right = heapRight(start);
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if (left < assoc) {
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assert(heapRank(set, start) >= heapRank(set, left));
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verifyHeap(set, left);
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}
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if (right < assoc) {
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assert(heapRank(set, start) >= heapRank(set, right));
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verifyHeap(set, right);
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}
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}
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void processRankIncrease(int set, int start) {
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int parent = heapParent(start);
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while (start > 0 && heapRank(set,parent) < heapRank(set,start)) {
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heapSwap(set, parent, start);
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start = parent;
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parent = heapParent(start);
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}
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}
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void processSet(int set);
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static const RefIndex InfiniteRef = 0x7fffffff;
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/** Memory reference trace. */
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MemTraceReader *trace;
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/** Cache heap for replacement. */
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std::vector<RefIndex> cacheHeap;
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/** The number of blocks in the cache. */
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const int numBlks;
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const int assoc;
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const int numSets;
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const int setMask;
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int misses;
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int hits;
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public:
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/**
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* Construct a OptCPU object.
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*/
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OptCPU(const std::string &name,
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MemTraceReader *_trace,
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int block_size,
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int cache_size,
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int assoc);
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/**
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* Perform the optimal replacement simulation.
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*/
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void tick();
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};
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#endif // __CPU_TRACE_OPT_CPU_HH__
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