cpu/base_cpu.cc: cpu/base_cpu.hh: Convert the CPU stuff to use a params struct cpu/memtest/memtest.cc: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. Don't have any default parameters. cpu/memtest/memtest.hh: The memory tester is really not a cpu, so don't derive from BaseCPU since it just makes things a pain in the butt. Keep track of max loads in the memtest class now that the base class doesn't do it for us. cpu/simple_cpu/simple_cpu.cc: Convert to use a params struct. remove default parameters cpu/simple_cpu/simple_cpu.hh: convert to use a params struct cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: this isn't really a cpu. don't derive from BaseCPU objects/MemTest.mpy: we only need one max_loads parameter sim/main.cc: Don't check for the number of CPUs since we may be doing something else going on. If we don't have anything to simulate, the simulator will exit anyway. --HG-- extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5
440 lines
14 KiB
C++
440 lines
14 KiB
C++
/*
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* Copyright (c) 2002-2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
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#include <iomanip>
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#include <set>
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#include <sstream>
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#include <string>
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#include <vector>
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#include "base/misc.hh"
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#include "base/statistics.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/memtest/memtest.hh"
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#include "mem/cache/base_cache.hh"
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#include "mem/functional_mem/main_memory.hh"
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#include "sim/builder.hh"
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#include "sim/sim_events.hh"
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#include "sim/stats.hh"
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using namespace std;
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int TESTER_ALLOCATOR=0;
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MemTest::MemTest(const string &name,
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MemInterface *_cache_interface,
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FunctionalMemory *main_mem,
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FunctionalMemory *check_mem,
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unsigned _memorySize,
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unsigned _percentReads,
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unsigned _percentCopies,
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unsigned _percentUncacheable,
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unsigned _progressInterval,
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unsigned _percentSourceUnaligned,
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unsigned _percentDestUnaligned,
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Addr _traceAddr,
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Counter _max_loads)
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: SimObject(name),
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tickEvent(this),
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cacheInterface(_cache_interface),
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mainMem(main_mem),
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checkMem(check_mem),
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size(_memorySize),
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percentReads(_percentReads),
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percentCopies(_percentCopies),
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percentUncacheable(_percentUncacheable),
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progressInterval(_progressInterval),
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nextProgressMessage(_progressInterval),
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percentSourceUnaligned(_percentSourceUnaligned),
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percentDestUnaligned(percentDestUnaligned),
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maxLoads(_max_loads)
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{
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vector<string> cmd;
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cmd.push_back("/bin/ls");
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vector<string> null_vec;
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xc = new ExecContext(NULL, 0, mainMem, 0);
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blockSize = cacheInterface->getBlockSize();
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blockAddrMask = blockSize - 1;
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traceBlockAddr = blockAddr(_traceAddr);
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//setup data storage with interesting values
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uint8_t *data1 = new uint8_t[size];
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uint8_t *data2 = new uint8_t[size];
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uint8_t *data3 = new uint8_t[size];
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memset(data1, 1, size);
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memset(data2, 2, size);
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memset(data3, 3, size);
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curTick = 0;
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baseAddr1 = 0x100000;
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baseAddr2 = 0x400000;
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uncacheAddr = 0x800000;
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// set up intial memory contents here
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mainMem->prot_write(baseAddr1, data1, size);
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checkMem->prot_write(baseAddr1, data1, size);
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mainMem->prot_write(baseAddr2, data2, size);
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checkMem->prot_write(baseAddr2, data2, size);
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mainMem->prot_write(uncacheAddr, data3, size);
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checkMem->prot_write(uncacheAddr, data3, size);
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delete [] data1;
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delete [] data2;
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delete [] data3;
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// set up counters
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noResponseCycles = 0;
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numReads = 0;
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tickEvent.schedule(0);
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id = TESTER_ALLOCATOR++;
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}
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static void
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printData(ostream &os, uint8_t *data, int nbytes)
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{
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os << hex << setfill('0');
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// assume little-endian: print bytes from highest address to lowest
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for (uint8_t *dp = data + nbytes - 1; dp >= data; --dp) {
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os << setw(2) << (unsigned)*dp;
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}
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os << dec;
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}
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void
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MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
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{
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//Remove the address from the list of outstanding
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std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->paddr);
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assert(removeAddr != outstandingAddrs.end());
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outstandingAddrs.erase(removeAddr);
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switch (req->cmd) {
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case Read:
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if (memcmp(req->data, data, req->size) != 0) {
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cerr << name() << ": on read of 0x" << hex << req->paddr
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<< " (0x" << hex << blockAddr(req->paddr) << ")"
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<< "@ cycle " << dec << curTick
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<< ", cache returns 0x";
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printData(cerr, req->data, req->size);
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cerr << ", expected 0x";
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printData(cerr, data, req->size);
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cerr << endl;
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fatal("");
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}
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numReads++;
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numReadsStat++;
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if (numReads == nextProgressMessage) {
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ccprintf(cerr, "%s: completed %d read accesses @%d\n",
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name(), numReads, curTick);
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nextProgressMessage += progressInterval;
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}
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if (numReads >= maxLoads)
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SimExit(curTick, "Maximum number of loads reached!");
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break;
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case Write:
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numWritesStat++;
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break;
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case Copy:
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//Also remove dest from outstanding list
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removeAddr = outstandingAddrs.find(req->dest);
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assert(removeAddr != outstandingAddrs.end());
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outstandingAddrs.erase(removeAddr);
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numCopiesStat++;
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break;
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default:
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panic("invalid command");
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}
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if (blockAddr(req->paddr) == traceBlockAddr) {
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cerr << name() << ": completed "
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<< (req->cmd.isWrite() ? "write" : "read")
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<< " access of "
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<< dec << req->size << " bytes at address 0x"
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<< hex << req->paddr
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<< " (0x" << hex << blockAddr(req->paddr) << ")"
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<< ", value = 0x";
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printData(cerr, req->data, req->size);
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cerr << " @ cycle " << dec << curTick;
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cerr << endl;
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}
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noResponseCycles = 0;
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delete [] data;
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}
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void
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MemTest::regStats()
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{
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using namespace Stats;
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numReadsStat
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.name(name() + ".num_reads")
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.desc("number of read accesses completed")
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;
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numWritesStat
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.name(name() + ".num_writes")
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.desc("number of write accesses completed")
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;
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numCopiesStat
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.name(name() + ".num_copies")
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.desc("number of copy accesses completed")
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;
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}
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void
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MemTest::tick()
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{
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if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + 1);
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if (++noResponseCycles >= 500000) {
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cerr << name() << ": deadlocked at cycle " << curTick << endl;
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fatal("");
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}
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if (cacheInterface->isBlocked()) {
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return;
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}
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//make new request
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unsigned cmd = rand() % 100;
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unsigned offset1 = random() % size;
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unsigned offset2 = random() % size;
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unsigned base = random() % 2;
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uint64_t data = random();
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unsigned access_size = random() % 4;
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unsigned cacheable = rand() % 100;
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unsigned source_align = rand() % 100;
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unsigned dest_align = rand() % 100;
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//If we aren't doing copies, use id as offset, and do a false sharing
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//mem tester
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if (percentCopies == 0) {
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//We can eliminate the lower bits of the offset, and then use the id
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//to offset within the blks
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offset1 &= ~63; //Not the low order bits
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offset1 += id;
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access_size = 0;
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}
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MemReqPtr req = new MemReq();
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if (cacheable < percentUncacheable) {
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req->flags |= UNCACHEABLE;
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req->paddr = uncacheAddr + offset1;
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} else {
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req->paddr = ((base) ? baseAddr1 : baseAddr2) + offset1;
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}
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bool probe = (rand() % 2 == 1) && !req->isUncacheable();
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probe = false;
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req->size = 1 << access_size;
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req->data = new uint8_t[req->size];
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req->paddr &= ~(req->size - 1);
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req->time = curTick;
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req->xc = xc;
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if (cmd < percentReads) {
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// read
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//For now we only allow one outstanding request per addreess per tester
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//This means we assume CPU does write forwarding to reads that alias something
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//in the cpu store buffer.
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if (outstandingAddrs.find(req->paddr) != outstandingAddrs.end()) return;
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else outstandingAddrs.insert(req->paddr);
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req->cmd = Read;
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uint8_t *result = new uint8_t[8];
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checkMem->access(Read, req->paddr, result, req->size);
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if (blockAddr(req->paddr) == traceBlockAddr) {
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cerr << name()
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<< ": initiating read "
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<< ((probe)?"probe of ":"access of ")
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<< dec << req->size << " bytes from addr 0x"
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<< hex << req->paddr
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<< " (0x" << hex << blockAddr(req->paddr) << ")"
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<< " at cycle "
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<< dec << curTick << endl;
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}
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if (probe) {
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cacheInterface->probeAndUpdate(req);
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completeRequest(req, result);
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} else {
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req->completionEvent = new MemCompleteEvent(req, result, this);
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cacheInterface->access(req);
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}
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} else if (cmd < (100 - percentCopies)){
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// write
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//For now we only allow one outstanding request per addreess per tester
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//This means we assume CPU does write forwarding to reads that alias something
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//in the cpu store buffer.
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if (outstandingAddrs.find(req->paddr) != outstandingAddrs.end()) return;
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else outstandingAddrs.insert(req->paddr);
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req->cmd = Write;
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memcpy(req->data, &data, req->size);
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checkMem->access(Write, req->paddr, req->data, req->size);
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if (blockAddr(req->paddr) == traceBlockAddr) {
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cerr << name() << ": initiating write "
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<< ((probe)?"probe of ":"access of ")
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<< dec << req->size << " bytes (value = 0x";
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printData(cerr, req->data, req->size);
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cerr << ") to addr 0x"
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<< hex << req->paddr
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<< " (0x" << hex << blockAddr(req->paddr) << ")"
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<< " at cycle "
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<< dec << curTick << endl;
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}
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if (probe) {
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cacheInterface->probeAndUpdate(req);
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completeRequest(req, NULL);
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} else {
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req->completionEvent = new MemCompleteEvent(req, NULL, this);
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cacheInterface->access(req);
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}
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} else {
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// copy
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Addr source = ((base) ? baseAddr1 : baseAddr2) + offset1;
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Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2;
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if (outstandingAddrs.find(source) != outstandingAddrs.end()) return;
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else outstandingAddrs.insert(source);
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if (outstandingAddrs.find(dest) != outstandingAddrs.end()) return;
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else outstandingAddrs.insert(dest);
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if (source_align >= percentSourceUnaligned) {
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source = blockAddr(source);
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}
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if (dest_align >= percentDestUnaligned) {
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dest = blockAddr(dest);
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}
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req->cmd = Copy;
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req->flags &= ~UNCACHEABLE;
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req->paddr = source;
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req->dest = dest;
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delete [] req->data;
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req->data = new uint8_t[blockSize];
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req->size = blockSize;
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if (source == traceBlockAddr || dest == traceBlockAddr) {
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cerr << name()
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<< ": initiating copy of "
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<< dec << req->size << " bytes from addr 0x"
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<< hex << source
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<< " (0x" << hex << blockAddr(source) << ")"
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<< " to addr 0x"
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<< hex << dest
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<< " (0x" << hex << blockAddr(dest) << ")"
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<< " at cycle "
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<< dec << curTick << endl;
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}
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cacheInterface->access(req);
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uint8_t result[blockSize];
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checkMem->access(Read, source, &result, blockSize);
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checkMem->access(Write, dest, &result, blockSize);
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}
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}
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void
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MemCompleteEvent::process()
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{
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tester->completeRequest(req, data);
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delete this;
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}
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const char *
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MemCompleteEvent::description()
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{
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return "memory access completion";
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
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SimObjectParam<BaseCache *> cache;
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SimObjectParam<FunctionalMemory *> main_mem;
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SimObjectParam<FunctionalMemory *> check_mem;
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Param<unsigned> memory_size;
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Param<unsigned> percent_reads;
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Param<unsigned> percent_copies;
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Param<unsigned> percent_uncacheable;
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Param<unsigned> progress_interval;
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Param<unsigned> percent_source_unaligned;
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Param<unsigned> percent_dest_unaligned;
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Param<Addr> trace_addr;
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Param<Counter> max_loads;
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END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
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BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
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INIT_PARAM(cache, "L1 cache"),
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INIT_PARAM(main_mem, "hierarchical memory"),
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INIT_PARAM(check_mem, "check memory"),
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INIT_PARAM(memory_size, "memory size"),
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INIT_PARAM(percent_reads, "target read percentage"),
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INIT_PARAM(percent_copies, "target copy percentage"),
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INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
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INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
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INIT_PARAM(percent_source_unaligned,
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"percent of copy source address that are unaligned"),
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INIT_PARAM(percent_dest_unaligned,
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"percent of copy dest address that are unaligned"),
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INIT_PARAM(trace_addr, "address to trace"),
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INIT_PARAM(max_loads, "terminate when we have reached this load count")
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END_INIT_SIM_OBJECT_PARAMS(MemTest)
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CREATE_SIM_OBJECT(MemTest)
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{
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return new MemTest(getInstanceName(), cache->getInterface(), main_mem,
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check_mem, memory_size, percent_reads, percent_copies,
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percent_uncacheable, progress_interval,
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percent_source_unaligned, percent_dest_unaligned,
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trace_addr, max_loads);
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}
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REGISTER_SIM_OBJECT("MemTest", MemTest)
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