branch prediction, and makes memory dependence work properly. SConscript: Added return address stack, tournament predictor. cpu/base_cpu.cc: Added debug break and print statements. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Comment out possibly unneeded variables. cpu/beta_cpu/2bit_local_pred.cc: 2bit predictor no longer speculatively updates itself. cpu/beta_cpu/alpha_dyn_inst.hh: Comment formatting. cpu/beta_cpu/alpha_full_cpu.hh: Formatting cpu/beta_cpu/alpha_full_cpu_builder.cc: Added new parameters for branch predictors, and IQ parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Register stats. cpu/beta_cpu/alpha_params.hh: Added parameters for IQ, branch predictors, and store sets. cpu/beta_cpu/bpred_unit.cc: Removed one class. cpu/beta_cpu/bpred_unit.hh: Add in RAS, stats. Changed branch predictor unit functionality so that it holds a history of past branches so it can update, and also hold a proper history of the RAS so it can be restored on branch mispredicts. cpu/beta_cpu/bpred_unit_impl.hh: Added in stats, history of branches, RAS. Now bpred unit actually modifies the instruction's predicted next PC. cpu/beta_cpu/btb.cc: Add in sanity checks. cpu/beta_cpu/comm.hh: Add in communication where needed, remove it where it's not. cpu/beta_cpu/commit.hh: cpu/beta_cpu/rename.hh: cpu/beta_cpu/rename_impl.hh: Add in stats. cpu/beta_cpu/commit_impl.hh: Stats, update what is sent back on branch mispredict. cpu/beta_cpu/cpu_policy.hh: Change the bpred unit being used. cpu/beta_cpu/decode.hh: cpu/beta_cpu/decode_impl.hh: Stats. cpu/beta_cpu/fetch.hh: Stats, change squash so it can handle squashes from decode differently than squashes from commit. cpu/beta_cpu/fetch_impl.hh: Add in stats. Change how a cache line is fetched. Update to work with caches. Also have separate functions for different behavior if squash is coming from decode vs commit. cpu/beta_cpu/free_list.hh: Remove some old comments. cpu/beta_cpu/full_cpu.cc: cpu/beta_cpu/full_cpu.hh: Added function to remove instructions from back of instruction list until a certain sequence number. cpu/beta_cpu/iew.hh: Stats, separate squashing behavior due to branches vs memory. cpu/beta_cpu/iew_impl.hh: Stats, separate squashing behavior for branches vs memory. cpu/beta_cpu/inst_queue.cc: Debug stuff cpu/beta_cpu/inst_queue.hh: Stats, change how mem dep unit works, debug stuff cpu/beta_cpu/inst_queue_impl.hh: Stats, change how mem dep unit works, debug stuff. Also add in parameters that used to be hardcoded. cpu/beta_cpu/mem_dep_unit.hh: cpu/beta_cpu/mem_dep_unit_impl.hh: Add in stats, change how memory dependence unit works. It now holds the memory instructions that are waiting for their memory dependences to resolve. It provides which instructions are ready directly to the IQ. cpu/beta_cpu/regfile.hh: Fix up sanity checks. cpu/beta_cpu/rename_map.cc: Fix loop variable type. cpu/beta_cpu/rob_impl.hh: Remove intermediate DynInstPtr cpu/beta_cpu/store_set.cc: Add in debugging statements. cpu/beta_cpu/store_set.hh: Reorder function arguments to match the rest of the calls. --HG-- extra : convert_revision : aabf9b1fecd1d743265dfc3b174d6159937c6f44
254 lines
6.4 KiB
C++
254 lines
6.4 KiB
C++
#include "cpu/beta_cpu/store_set.hh"
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#include "base/trace.hh"
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StoreSet::StoreSet(int _SSIT_size, int _LFST_size)
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: SSIT_size(_SSIT_size), LFST_size(_LFST_size)
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{
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DPRINTF(StoreSet, "StoreSet: Creating store set object.\n");
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DPRINTF(StoreSet, "StoreSet: SSIT size: %i, LFST size: %i.\n",
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SSIT_size, LFST_size);
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SSIT = new SSID[SSIT_size];
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validSSIT.resize(SSIT_size);
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for (int i = 0; i < SSIT_size; ++i)
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validSSIT[i] = false;
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LFST = new InstSeqNum[LFST_size];
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validLFST.resize(LFST_size);
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SSCounters = new int[LFST_size];
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for (int i = 0; i < LFST_size; ++i)
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{
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validLFST[i] = false;
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SSCounters[i] = 0;
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}
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index_mask = SSIT_size - 1;
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offset_bits = 2;
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}
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void
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StoreSet::violation(Addr store_PC, Addr load_PC)
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{
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int load_index = calcIndex(load_PC);
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int store_index = calcIndex(store_PC);
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assert(load_index < SSIT_size && store_index < SSIT_size);
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bool valid_load_SSID = validSSIT[load_index];
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bool valid_store_SSID = validSSIT[store_index];
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if (!valid_load_SSID && !valid_store_SSID) {
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// Calculate a new SSID here.
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SSID new_set = calcSSID(load_PC);
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validSSIT[load_index] = true;
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SSIT[load_index] = new_set;
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validSSIT[store_index] = true;
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SSIT[store_index] = new_set;
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assert(new_set < LFST_size);
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SSCounters[new_set]++;
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DPRINTF(StoreSet, "StoreSet: Neither load nor store had a valid "
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"storeset, creating a new one: %i for load %#x, store %#x\n",
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new_set, load_PC, store_PC);
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} else if (valid_load_SSID && !valid_store_SSID) {
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SSID load_SSID = SSIT[load_index];
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validSSIT[store_index] = true;
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SSIT[store_index] = load_SSID;
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assert(load_SSID < LFST_size);
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SSCounters[load_SSID]++;
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DPRINTF(StoreSet, "StoreSet: Load had a valid store set. Adding "
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"store to that set: %i for load %#x, store %#x\n",
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load_SSID, load_PC, store_PC);
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} else if (!valid_load_SSID && valid_store_SSID) {
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SSID store_SSID = SSIT[store_index];
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validSSIT[load_index] = true;
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SSIT[load_index] = store_SSID;
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// Because we are having a load point to an already existing set,
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// the size of the store set is not incremented.
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DPRINTF(StoreSet, "StoreSet: Store had a valid store set: %i for "
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"load %#x, store %#x\n",
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store_SSID, load_PC, store_PC);
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} else {
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SSID load_SSID = SSIT[load_index];
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SSID store_SSID = SSIT[store_index];
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assert(load_SSID < LFST_size && store_SSID < LFST_size);
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int load_SS_size = SSCounters[load_SSID];
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int store_SS_size = SSCounters[store_SSID];
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// If the load has the bigger store set, then assign the store
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// to the same store set as the load. Otherwise vice-versa.
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if (load_SS_size > store_SS_size) {
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SSIT[store_index] = load_SSID;
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SSCounters[load_SSID]++;
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SSCounters[store_SSID]--;
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DPRINTF(StoreSet, "StoreSet: Load had bigger store set: %i; "
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"for load %#x, store %#x\n",
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load_SSID, load_PC, store_PC);
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} else {
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SSIT[load_index] = store_SSID;
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SSCounters[store_SSID]++;
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SSCounters[load_SSID]--;
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DPRINTF(StoreSet, "StoreSet: Store had bigger store set: %i; "
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"for load %#x, store %#x\n",
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store_SSID, load_PC, store_PC);
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}
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}
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}
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void
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StoreSet::insertLoad(Addr load_PC, InstSeqNum load_seq_num)
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{
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// Does nothing.
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return;
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}
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void
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StoreSet::insertStore(Addr store_PC, InstSeqNum store_seq_num)
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{
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int index = calcIndex(store_PC);
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int store_SSID;
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assert(index < SSIT_size);
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if (!validSSIT[index]) {
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// Do nothing if there's no valid entry.
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return;
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} else {
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store_SSID = SSIT[index];
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assert(store_SSID < LFST_size);
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// Update the last store that was fetched with the current one.
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LFST[store_SSID] = store_seq_num;
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validLFST[store_SSID] = 1;
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DPRINTF(StoreSet, "Store %#x updated the LFST, SSID: %i\n",
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store_PC, store_SSID);
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}
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}
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InstSeqNum
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StoreSet::checkInst(Addr PC)
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{
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int index = calcIndex(PC);
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int inst_SSID;
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assert(index < SSIT_size);
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if (!validSSIT[index]) {
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DPRINTF(StoreSet, "Inst %#x with index %i had no SSID\n",
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PC, index);
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// Return 0 if there's no valid entry.
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return 0;
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} else {
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inst_SSID = SSIT[index];
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assert(inst_SSID < LFST_size);
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if (!validLFST[inst_SSID]) {
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DPRINTF(StoreSet, "Inst %#x with index %i and SSID %i had no "
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"dependency\n", PC, index, inst_SSID);
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return 0;
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} else {
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DPRINTF(StoreSet, "Inst %#x with index %i and SSID %i had LFST "
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"inum of %i\n", PC, index, inst_SSID, LFST[inst_SSID]);
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return LFST[inst_SSID];
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}
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}
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}
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void
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StoreSet::issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
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{
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// This only is updated upon a store being issued.
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if (!is_store) {
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return;
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}
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int index = calcIndex(issued_PC);
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int store_SSID;
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assert(index < SSIT_size);
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// Make sure the SSIT still has a valid entry for the issued store.
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if (!validSSIT[index]) {
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return;
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}
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store_SSID = SSIT[index];
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assert(store_SSID < LFST_size);
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// If the last fetched store in the store set refers to the store that
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// was just issued, then invalidate the entry.
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if (validLFST[store_SSID] && LFST[store_SSID] == issued_seq_num) {
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DPRINTF(StoreSet, "StoreSet: store invalidated itself in LFST.\n");
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validLFST[store_SSID] = false;
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}
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}
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void
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StoreSet::squash(InstSeqNum squashed_num)
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{
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// Not really sure how to do this well.
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// Generally this is small enough that it should be okay; short circuit
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// evaluation should take care of invalid entries.
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DPRINTF(StoreSet, "StoreSet: Squashing until inum %i\n",
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squashed_num);
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for (int i = 0; i < LFST_size; ++i) {
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if (validLFST[i] && LFST[i] < squashed_num) {
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validLFST[i] = false;
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}
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}
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}
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void
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StoreSet::clear()
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{
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for (int i = 0; i < SSIT_size; ++i) {
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validSSIT[i] = false;
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}
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for (int i = 0; i < LFST_size; ++i) {
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validLFST[i] = false;
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}
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}
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